Processor Exception Vector Encoding - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
CPU Watchpoints
CPU
SPR Selection
CPU
GTM Watchpoints
GTM
Nexus Watchpoints
NAR
Counters/Timers
16
Decoder
processor_exception
63.6.2

Processor exception vector encoding

Active-high input signals from the CPU indicate the particular exception being processed
when the CPU exception enable signal is asserted. These signals can be used for debug
triggering mechanisms. The SPU captures the CPU exception vector whenever the CPU
exception enable signal is asserted and the SPU uses the exception vector as an input
condition as shown in
be byte swapped before they are programmed to the CPUn field of the CnPEVP (n = 0–0)
registers as shown in
1856/2058
Figure 1097. Input Mux unit block diagram
64 Muxes
32
1
15
12
1
3
1
DCI EVTI
16
1
DCI EVTO
DCI System Halt
Decoder
2
Table 1040. The CPU exception vector values from the CPUs must
Table 1040.
DocID027809 Rev 4
16 - 64x 1
64 .
64
64 .
}
SPU to DCI
Interrupt processor
8
CPU
Context Load/Save CPU
RM0400
slu_event[0]
STATE
16
LOGIC
UNIT 0
16
STATE
LOGIC
UNIT 7
slu_event[7]