Sequence Processing Unit (Spu) - STMicroelectronics SPC572L series Reference Manual

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Sequence Processing Unit (SPU)

63.1 Introduction
The Sequence Processing Unit (SPU) provides an on-device trigger functions similar to
those found on a logic analyzer. In a complex SoC, performance monitor functions are
available at two levels: system level and CPU level. Complex trigger and system
performance monitor functions are implemented in the SPU module. System level
performance monitor functions are integrated into the SPU complex trigger logic, and thus
allow counting and timing of any debug trigger combinations supported by the SPU.
Various clients such as the cores, GTM, or crossbar switch, generate watchpoints and
triggers when operating in their debug mode. The SPU collects these triggers (such as
interrupt occurrence, address watchpoint, and so on) and uses them as conditions to
sequence through states, with resultant actions (such as start/stop trace, start/stop counter,
capture timebase, and so on). The SPU provides the capability to create complex debug
triggers. By configuring each of the events to trigger specific actions, complex logic-
analyzer-like behavior can be achieved, providing vital real-time visibility and debug ability
of the activities of the system.
63.1.1 SPU block diagram
Figure 1062
SPU
shows a top-level block diagram of the SPU.
Figure 1062. SPU block diagram
Nexus-Client
GTM
Triggers from each source
Input Mux Unit
Synchronization Unit
State Logic Unit
DocID027809 Rev 4
Sequence Processing Unit (SPU)
Nexus-Client
CPU(2)
Clocks and Reset
JTAG I/F
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