Fec Frame Transmission - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
Signal description
Receive Clock
Receive Data Valid
Receive Data
48.5.9

FEC frame transmission

The Ethernet transmitter is designed to work with almost no intervention from software. After
ECR[ETHER_EN] is set and data appears in the transmit FIFO, the Ethernet MAC can
transmit onto the network. The Ethernet controller transmits bytes least significant bit (lsb)
first.
When the transmit FIFO fills to the watermark (defined by TFWR), MAC transmit logic
asserts FEC_TXEN and starts transmitting the (PA) sequence, the start frame delimiter
(SFD), and then the frame information from the FIFO. However, the controller defers the
transmission if the network is busy (FEC_CRS is asserted). Before transmitting, the
controller waits for carrier sense to become inactive, then determines if carrier sense stays
inactive for 60 bit times. If so, transmission begins after waiting an additional 36 bit times (96
bit times after carrier sense originally became inactive). See
Transmission
If a collision occurs during transmission of the frame (half duplex mode), the Ethernet
controller follows the specified backoff procedures and attempts to retransmit the frame until
the retry limit is reached. The transmit FIFO stores at least the first 64 bytes of the transmit
frame, so they do not have to be retrieved from system memory in case of a collision. This
improves bus utilization and latency in case immediate retransmission is necessary.
When all the frame data is transmitted, FCS (frame check sequence) or 32-bit cyclic
redundancy check (CRC) bytes are appended if the TC bit is set in the transmit frame
control word. If the ABC bit is set in the transmit frame control word, a bad CRC is appended
to the frame data regardless of the TC bit value. Following the transmission of the CRC, the
Ethernet controller writes the frame status information to the MIB block. Transmit logic
automatically pads short frames (if the TC bit in the transmit buffer descriptor for the end of
frame buffer is set).
Settings in the EIMR determine interrupts generated to the buffer (TXB) and frame (TXF).
The transmit error interrupts are HBERR, BABT, LC, RL, and UN. If the transmit frame
length exceeds MAX_FL bytes, BABT interrupt is asserted. However, the entire frame is
transmitted (no truncation).
To pause transmission, set TCR[GTS] (graceful transmit stop). The FEC transmitter stops
immediately if transmission is not in progress; otherwise, it continues transmission until the
current frame finishes or terminates with a collision. After the transmitter has stopped, the
GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC
resumes transmission with the next frame.
48.5.9.1 Duplicate frame transmission
The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data
continuously until the transmit FIFO is full. It does not determine whether the TxBD to be
1348/2058
Table 786. 7-Wire mode configuration(Continued)
errors, for more details.
DocID027809 Rev 4
EMAC pin
FEC_RXCLK
FEC_RXDV
FEC_RXD[0]
Section 48.5.19.1:
RM0400