Table 534. Timeout Counter Configuration Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
44.3.5.2.9 Timestamp Counter Value Register (TSCV)
Address: 0x0024
0 1
R
W
Reset 0 0
16 17 18
R
W
Reset 0 0
Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not
caused by write access to TSCV.
44.3.5.2.10 Timeout Counter Configuration Register (TOCC)
For a description of the Timeout Counter see <Cross Refs>Section 44.3.9, Timeout counter.
Address: 0x0028
0 1
R
W
Reset 1 1
16 17 18
R
W
Reset 0 0
1. These are protected write (P) bits which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0
[INIT] of CCCR register are set to "1".

Table 534. Timeout Counter Configuration Field Descriptions

Field
0:15 Timeout Period
TOP[15:0] Start value of the Timeout Counter (down-counter). Configures the Timeout Period.
16:28 Reserved
2 3 4 5
0 0 0 0
19 20 21
0 0 0 0
Figure 480. Timestamp counter value register
2 3 4 5
1 1 1 1
19 20 21
0 0 0 0
Figure 481. Timeout counter configuration register
6 7 8 9
0
0 0 0 0
22 23 24 25
TSC
w1c
0 0 0 0
6 7 8 9
(1)
TOP
1 1 1 1
22 23 24 25
0
0 0 0 0
Description
DocID027809 Rev 4
CAN Subsystem
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
10 11 12 13
1 1 1 1
26 27 28 29
TOS
0 0 0 0
Access: w1c
14 15
0 0
30 31
0 0
Access: RP
14 15
1 1
30 31
ETOC
1
1
0 0
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