Table 301. Lock0 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Embedded Flash Memory (MP55)
29.3.2.3 Lock 0 register (LOCK0)
The LOCK0 (Low/Mid Address Space Block Locking) register provides a means of
protecting blocks from being modified. LOWLOCK and MIDLOCK bits corresponding to non
existent blocks are read as '1'.
To determine the effective status of the Low/Mid Address Space, combine (Or) LOCK0 with
sidebands:
•
f90_plock0 – in order to evaluate protection against programming.
•
f90_elock0 – in order to evaluate protection against erase.
The effect of programming or erasing a block protected with LOCK0 is that no modification
occurs and PEG is set to '1'.
Address
0x0010
:
0 1
R 0
W
Reset 1 0
16 17
R
W
Reset 1 1
Field
UTEST NVM block lock (Read/Write)
This bit is used to lock the UTEST NVM from programming (UTEST NVM is not erasable).
The LOCK field is not writable:
– Once an Interlock Write is completed until MCR[DONE] is set.
0
– If a high voltage operation is suspended.
TSLOCK
The default value of the TSLOCK bit is locked.
The effective status of the UTEST protection is done combining (ORed) LOCK0[TSLOCK]
with sidebands f90_plock0.31 in order to evaluate protection against program.
0 Test Address Space Block is unlocked and can be modified.
1 Test Address Space Block is locked and cannot be modified.
Reserved (read only).
1
Writing to this bit has no effect and Reads always return 0.
610/2058
2 3 4 5
1 1 1 1
18 19 20 21
1 1 1 1
Figure 256. Locking 0 register (LOCK0)

Table 301. LOCK0 field descriptions

DocID027809 Rev 4
6 7 8 9
LOWLOCK
1 1 1 1
22 23 24 25
MIDLOCK
1 1 1 1
Description
Access: User Read/Write
10 11 12 13
1 1 1 1
26 27 28 29
1 1 1 1
RM0400
14 15
1 1
30 31
1 1