Using Debug Resources For Stack Limit Checking - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
register. See the "Data Acquisition Messaging" section in the Core (e200z215An3) Nexus 3
Module chapter for details.
The DDAM register is shown in
0 1 2 3 4 5 6
Figure 1000. Debug Data Acquisition Message (DDAM) register
1. Reset by processor reset p_reset_b if EDBCR0
EDBRAC0 masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by
EDBRAC0 will be reset by p_reset_b.
Table 951
Bit Name
0:31 DDAM
57.4

Using debug resources for stack limit checking

The DAC1,2 and DAC3,4 resources can be used for stack overflow/underflow detection
when not being used as a hardware or software debug resource. Stack limit checking is
available regardless of EDM or IDM mode, and when resources used for stack limit
checking are owned by software, will utilize a DSI or machine check exception. Software-
owned stack limit checking does not require IDM to be set. Hardware owned stack limit
checking requires EDM to be set.
When stack limit checking is enabled, and DAC resources used for stack limit checking are
owned by software, DAC events are not generated for resources configured to perform
stack limit checking, and no DBSR DAC status flag will be set due to a detected stack limit
violation. Instead, depending on the processor mode, a data storage interrupt or a machine
check exception is signaled. When stack limit checking is enabled, and DAC resources
used for stack limit checking are owned by hardware, DAC events will be generated for
resources configured to perform stack limit checking, and the EDBSR0 DAC status flag will
be set due to a detected stack limit violation, causing entry into debug halted mode in the
same way as a DAC exception normally does. The only difference is that qualification of the
access address is performed as discussed in the next paragraph.
Stack limit checking is implemented in the same way as range compares using DAC1,2 or
3,4, or extended masking using DAC1 or DAC3, but qualify a load or store access address
with the use of GPR R1 as the base or index register used to compute an effective address
when a load or store instruction is executed. No stack limit checking is performed for
instructions that indicate GPR R1 is used to hold a decoration value (for decorated
load/store type instructions). When DAC resources configured to perform stack limit
checking are not owned by hardware, if a stack limit violation occurs when performing the
load or store, the access is aborted, and an error report machine check is generated, with
MCSRR0 pointing to the address of the load or store access that generated the stack
overflow/underflow. If DAC resources configured to perform stack limit checking are owned
1686/2058
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR 576; Reset
EDM
provides bit definitions for the Debug Data Acquisition Message Register.
Table 951. DDAM field descriptions
Value to be transmitted in a Data Acquisition Message (DQM) (supplied to Nexus 3 with
strobe)
DocID027809 Rev 4
Figure 1000.
DDAM
(1)
: 0x0
=0, as well as unconditionally by m_por. If EDBCR0
Description
RM0400
=1,
EDM