Table 981. Configuration Register 0 Format - STMicroelectronics SPC572L series Reference Manual

IEEE 1149.7 Compact JTAG Test Access Port Controller (CJTAG)
Bit
9
11
13:12
14
16:15
18:17
20:19
22:21
31:23
60.6.2.3.14 Configuration Register 0 (CNFG0)
Field Bit #
CNFG
3:0
(Class)
CNFG
7:4
(Revision)
CNFG
11:8
(Format)
1766/2058
Table 980. RDBACK register format(Continued)
Width Register Mnemonic
1 SGC
CGM
1 SSDE
2 TOPOL
1 SREDGE
2 DLYC
2 RDYC
2 APFC
2 STCKDC
11 Reserved

Table 981. Configuration Register 0 Format

Width Name
4 CLASS[3:0]
4 REV[3:0]
4 CNFGFMT[3:0]
DocID027809 Rev 4
Scan Group Candidate
Conditional Group Member
Scan Selection Directive Enable
Topology
Sampling Edge
Delay Control
Ready Control
Auxiliary Pin Functional Control
SYS_TCK Duty Cycle
Read as a logic 0
Description
TAP.7 Class
0000 – TAP.1 or TAP.7 Class T0
0001 – Class T1
0010 – Class T2
0011 – Class T3
0100 – Class T4
0101 – Class T5
TAP.7 specification revision.
Initial revision = all zeroes (0s)
0000 – Reserved
0001 – IEEE Std 1149.7-2008
0010 – 1111 - Reserved
Configuration Register Format
xxx1 – CNFG0[31:12] are implemented
xx1x – CNFG1 implemented
x1xx – CNFG2 implemented
1xxx – CNFG3 implemented
RM0400
Name