Figure 632. Dspi Usage In The Tsb Configuration - STMicroelectronics SPC572L series Reference Manual

RM0400
Figure 632
In the TSB configuration the DSPI is able to send from 4 to 66 bits MSC data frames (4 to 64
serialized data bits and up to 2 Data Selection zero bits). The serialized data bits source
can be either:
•
the DSPI DSI Alternate Serialization Data Register (DSPI_ASDR0/1), written by the
host software,
• parallel input pin states latched into the DSPI DSI Serialization Data Register
(DSPI_SDR0/1).
DSICR0[TXSS] bit or DSPI_SSR0/1 register bits define the source of the data.
The Least Significant Bits of the DSPI_ASDR0 or DSPI_SDR0 registers are selected to be
serialized if the data frame is set to less than 32 bits.
The PCS signals are driven together with SOUT. The t
available. Delay after Transfer (DT) is set in SCK clock periods as a binary number formed
by concatenation of the DSPI_CTARn PDT and DT fields plus one, allowing to set DT from 1
to 64 serial clock periods. DT field provides least significant bits and PDT field provides
most significant bits of the Delay after Transfer.
S C K
(C P O L = 0)
1
M aster S O U T
P C S
= from 1 to 64 T
t
DT
C o m m and F ram e = 4 to 32 bits
Data Frame = 4 to 64 bits
shows the signals used in the TSB interface.

Figure 632. DSPI usage in the TSB Configuration

Figure 633. TSB Downstream Frames
C om m and F ram e C om m and F ram e
A ctive P h ase
LSB
SCK
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
and t
CSC
A ctive P h ase
Invalid
0
LSB
t
DT
S election B it
delays are not
ASC
D ata F ram e
Invalid
t
DT
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