Table 518. Gtmintclr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
AEISREN AEI interface soft-reset control enable. The AEISREN bit enables the soft-reset of
the AEI interface that is controlled by AEISRST bit in the GTMMAEICR. Please refer to
15
Section 43.3.7, AEI Interface Software Reset Description
AEISREN
1 AEI soft-reset control is enabled
0 AEI soft-reset control is disabled
STPS Stop Mode Status. The STPS bit indicates the GTM-IP Module is in stop mode, or by
MDIS bit field setting or by stop line request. Please refer to
17
Description
STPS
1 GTM is in Stop Mode
0 Normal Mode
43.2.2.2 GTM Interrupts Clear Register (GTMINTCLR)
The GTMINTCLR contains the control bits to clear some specific interrupt request output.
.
Offset 0x000C8
0 1
R 0 0
W
Reset 0 0
16 17 18
R 0 0
W
Reset 0 0
GTMINTCLR register functions are as shown in
Field
INTCLR_PTR Interrupt Clear Pointer. This field value indicates / selects which interrupt will be
22–31
cleared. The correspondence between the number and the interrupt is given in
INTCLR_PTR[0:9]
Please refer to
Table 519. Correspondence between the INTCLR_PTR and the interrupts outputs
INTCLR_PTR[0:9]
HEX
0x000
0x001 to 0x2C1
0x2C2
0x2C3 to 0x2C5
Table 517. GTMMCR field descriptions(Continued)
for more details.
2 3 4 5
0 0 0 0
0 0 0 0
19 20 21
0 0 0 0
0 0 0 0
Figure 468. GTM Interrupts Clear Register (GTMINTCLR)

Table 518. GTMINTCLR field descriptions

Section 43.3.8, Interrupt and DMA Support Logic
DEC
0
1 to 705
706
707 to 709
DocID027809 Rev 4
GTM101 Integration (GTMINT) Module
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
INTCLR_PTR[0:9]
0 0 0 0
Table 518.
Description
Interrupt output signal to be cleared
No interrupt is selected
ipi_int_gtm_aru[0]–[2]
for more details.
Section 43.3.4, Stop Mode
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
for more details.
Reserved
ipi_int_gtm_aei
14 15
0 0
0 0
30 31
0 0
0 0
Table 519.
985/2058
995