Configuration Change Packets (Cp) - STMicroelectronics SPC572L series Reference Manual

RM0400
60.7.6

Configuration Change Packets (CP)

A Change Packet (CP) is composed of three element types:
•
Preamble – A 1-bit value that is a don't care. This bit facilitates a Standard to
Advanced Protocol change with some external tool implementations.
•
Body – Two or more bits representing one or more CP directives
–
–
–
–
•
Post amble – A 1-bit value that is a don't care. This bit facilitates and Advanced to
Standard Protocol change with some external tool implementations.
A minimum-length CP has a Preamble, a 2-bit Body, and a Post amble. This can be as
simple as four logic zero values.
60.7.7 Scan Packet
A Scan Packet defines the period of TMSC pin activity where control information exchanged
by the external tool and TAP.7 controller affects the TAPC state, except when the SP
precedes a Change Packet. The external tool should view the Scan Packet as:
•
Exchanging only the necessary TAPC information (TMS, TDI, and TDO or some subset
thereof)
• Causing an advance of the TAP.7 TAPC state when it is not followed by a Change
Packet.
•
Causing an advance of the STL TAPC state when it is not followed by a Change Packet
and when the STL is coupled.
With this perspective, the external tool views Scan Packets as running a virtual TAPC state
machine at the TAP.7 pins. The effects of each Scan Packet take effect when the Scan
Packet completes. The real TAP.7 and STL controller state machine states may change
state before or after the virtual state machine.
60.7.8 SP Format
A SP serially exchanges the TDI, TMS, and TDO or a subset thereof, between the external
tool and TAP.7 controller. Control information may be added to this exchange. A SP has
three parts:
•
Payload – Data + Control information (all scan formats), the payload content is varied
to trade-off performance and flexibility. RDY bit(s) within the payload are included with
some scan formats to provide the STL a means to stall progression of the TAPC state.
•
Delay – Control information (optional) providing separation of adjacent payloads in
time. Delay elements support simple external tool implementations where a delay
element is used to stall progression of the TAPC state while it develops a new SP
following the completion of the prior payload.
The header elements, delay elements, and control information within the payload element is
consumed by the TAP.7 controller. This and other control information within the SP payload
is not visible to the EPU and STL TAPCs.
IEEE 1149.7 Compact JTAG Test Access Port Controller (CJTAG)
00 – CP_END
01 – CP_NOP (extends the body by 1-bit)
10 – CP_NOP (extends the body by 1-bit)
11 – CP_RES (Generate a Type-3 TAP.7 controller reset coincident with the post
amble bit.
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