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Mode Entry Module (MC_ME)
Table 934. Core Control Register (ME_CCTL0) field descriptions(Continued)
Field
Core control during
10
0 core_0 is disabled with clock gated
RUN1
1 core_0 is running
Core control during
11
0 core_0 is frozen with clock gated
RUN0
1 core_0 is running
Core control during
12
0 core_0 is frozen with clock gated
DRUN
1 core_0 is running
Core control during
13
0 core_0 is frozen with clock gated
SAFE
1 core_0 is running
Core control during
14
0 core_0 is frozen with clock gated
TEST
1core_0 is running
15
Core control during
RESET
56.3.2.25 Core Control Registers (ME_CADDR0)
Address 0x1E0
0
1
2
R
W
Reset
X
X
X
16
17
18
R
W
Reset
X
X
X
This registers gives the boot address for core_0 and a bit for controlling whether core_0 is to
be reset on the next mode change that has core_0 configured to be running in the target
mode.
This register can be written only as a word and cannot be written after a mode change
request has been made until the mode transition has completed (i.e., while the S_MTRANS
bit of the ME_GS register = '1'). A write access to this register during this time will result in
the ICONF_CC flag in the ME_IS register being asserted.
Note:
The reset value of the ADDR field of the ME_CADDR0 is determined by the chip
configuration and boot mode.
1628/2058
RUN1
RUN0
DRUN
SAFE
TEST
RESET
— core_0 is always disabled during RESET.
3
4
5
6
X
X
X
X
19
20
21
22
ADDR[15:2]
X
X
X
X
Figure 982. Core Control Registers (ME_CADDR0)
DocID027809 Rev 4
Description
Access: User read, Supervisor read/write, Test read/write
7
8
9
10
ADDR[31:16]
X
X
X
X
23
24
25
26
X
X
X
X
RM0400
11
12
13
14
X
X
X
X
27
28
29
30
0
X
X
X
0
15
X
31
0
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