Table 144. Smpu0_Earn Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address SMPU0_EARn – FC01_0100h + (8d × n), where n = 0d to 15d
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 86. Error Address Register, Bus Master n (SMPU0_EARn)
Field
0–31 Error address
EADDR Indicates the reference address from bus master n that generated the access error
16.4.2.4 Error Detail Register, Bus Master n (SMPU0_EDRn)
When the SMPU detects an access error associated with bus master n, 32 bits of error
detail are captured in this read-only register and the corresponding bit in CESR0[MERR] is
set. Information on the faulting address is captured in the corresponding EARn register at
the same time.
Note: The corresponding EARn and EDRn registers contain information on the original access
error; subsequent errors associated with the given master are recorded as overruns in the
CESR1[MEOVR] field until the original error is processed.
Address SMPU0_EDRn – FC01_0104h + (8d × n), where n = 0d to 15d
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 87. Error Detail Register, Bus Master n (SMPU0_EDRn)
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0

Table 144. SMPU0_EARn field descriptions

2 3 4 5
0 0 0 0
18 19 20 21
EACD[15:8]
0 0 0 0
DocID027809 Rev 4
System Memory Protection Unit (SMPU)
6 7 8 9
EADDR
0 0 0 0
22 23 24 25
EADDR
0 0 0 0
Description
6 7 8 9
EACD[31:16]
0 0 0 0
22 23 24 25
1 EATTR
0 0 1 0
Access: Supervisor read-only
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
Access: Supervisor read-only
10 11 12 13
0 0 0 0
26 27 28 29
ERW EMN
0 0 0 0
14 15
0 0
30 31
0 0
14 15
0 0
30 31
0 0
333/2058
344