Table 684. Priority Levels For The Transmit Controller - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
TXDATA_P
LD
TXDATA_N
47.7.3.2 Arbitration
The arbitration block prioritizes between requests from multiple sources like:
•
S/W programmable registers
•
System side interface FIFO
• Rx interface controller
The level of priority for each request is shown in
LFAST Master
Request
Priority
LFAST interface
enable
Tx Interface
disabled
Tx Interface
speed
mode change
1266/2058
Figure 673. Transmit Controller Connections
TRANSMIT CONTROLLER
FRAMER
PISO
TX DATA FIFO
SystemSide Interface Module

Table 684. Priority Levels for the Transmit Controller

LFAST Slave
Priority
1 1
2 2
3 3
DocID027809 Rev 4
ARBITER
TX PACKET FIFO
Table 684.
Triggering Conditions
(at least one of the listed)
– LFAST interface enable is asserted
– LFAST interface enable is negated
– MCR[DRFEN] = 0
– MCR[TXEN] = 0
– MCR[DRFRST] = 1
– MCR[TXARBD] = 1
– LFAST Slave: ICLC frame with payload for "Disable Rx
interface" received
– SCR[TDR] is modified
– LFAST Slave: ICLC frame with payload for changing Rx
interface speed received
REGISTER
(Control
and
Status)