Table 259. Auxiliary Clock 7 Divider 0 Configuration Register (Cgm_Ac7_Dc0) Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Clock Generation Module (MC_CGM)
24.3.1.27 Auxiliary Clock 7 Divider 0 Configuration Register (CGM_AC7_DC0)
Address 0x08E8
0 1 2
R 0 0
DE
W
Reset 0 0 0
16 17 18
R 0 0 0
W
Reset 0 0 0
Figure 207. Auxiliary Clock 7 Divider 0 Configuration Register (CGM_AC7_DC0)
This register controls auxiliary clock 7 divider 0.
Note: Byte and half-word write accesses are not allowed for this register. Such accesses do not
result in an exception, but the value is not loaded with the new value.

Table 259. Auxiliary Clock 7 Divider 0 Configuration Register (CGM_AC7_DC0) field descriptions

Field
Divider Enable
0
0 Disable auxiliary clock 7 divider 0
DE
1 Enable auxiliary clock 7 divider 0
1–6 Reserved
Divider Division Value — The resultant SYSCLK1 pin clock will have a period 'DIV + 1' times that of
7–15
auxiliary clock 7. If DE is set to 0 (divider 0 is disabled), any write access to the DIV field is ignored and
DIV
the SYSCLK1 pin clock remains disabled.
16–31 Reserved
24.3.1.28 Auxiliary Clock 8 Select Control Register (CGM_AC8_SC)
Address 0x0900
0 1 2
R 0 0 0
W
Reset 0 0 0
16 17 18
R 0 0 0
W
Reset 0 0 0
Figure 208. Auxiliary Clock 8 Select Control Register (CGM_AC8_SC)
This register is used to select the current clock source for the following clocks:
•
undivided: (unused)
•
divided by auxiliary clock 8 divider 0: CCCU clock
520/2058
Access: User read/write, Supervisor read/write, Test read/write
3 4 5 6
0 0 0 0
0 0 0 0
19 20 21 22
0 0 0 0
0 0 0 0
Access: User read/write, Supervisor read/write, Test read/write
3 4 5 6
0
SELCTL
0 0 0 0
19 20 21 22
0 0 0 0
0 0 0 0
DocID027809 Rev 4
7 8 9 10
0 0 0 0
23 24 25 26
0 0 0 0
0 0 0 0
Description
7 8 9 10
0 0 0
1 0 0 0
23 24 25 26
0 0 0 0
0 0 0 0
RM0400
11 12 13 14
DIV
0 0 0 0
27 28 29 30
0 0 0 0
0 0 0 0
11 12 13 14
0 0 0 0
0 0 0 0
27 28 29 30
0 0 0 0
0 0 0 0
15
0
31
0
0
15
0
0
31
0
0