Message Ram - STMicroelectronics SPC572L series Reference Manual

CAN Subsystem
Table 567. Tx Event FIFO Status field description(Continued)
Field
[11:15]
EFPI
[16:18]
[19:23]
EFGI
[24:25]
[26:31]
EFFL
44.3.5.2.43 Tx Event FIFO Acknowledge Register (TXEFA)
Address: 0x00F8
0 1
R
W
Reset 0 0
16 17 18
R
W
Reset 0 0
Field
[0:26] Reserved.
Event FIFO Acknowledge Index.
After the Host has read an element or a sequence of elements from the Tx Event FIFO it has
[27:31]
to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx
EFAI
Event FIFO Get Index TXEFS[EFGI] to EFAI + 1 and update the FIFO 0 Fill Level
TXEFS[ EFFL].
44.3.6

Message RAM

The Message RAM has a width of 32 bits. In case parity checking or ECC is used a
respective number of bits has to be added to each word. The M_CAN module can be
configured to allocate up to 1216 words in the Message RAM. It is not necessary to
configure each of the sections listed in the following figure, nor is there any restriction with
respect to the sequence of the sections.
1046/2058
Event FIFO Put Index.
Tx Event FIFO write index pointer, range 0 to 31.
Reserved
Event FIFO Get Index.
Tx Event FIFO read index pointer, range 0 to 31.
Reserved.
Event FIFO Fill Level.
Number of elements stored in Tx Event FIFO, range 0 to 32.
2 3 4 5
0 0 0 0
19 20 21
0
0 0 0 0
Figure 513. Tx Event FIFO Acknowledge register
Table 568. Tx Event FIFO Acknowledge field description
Description
6 7 8 9
0
0 0 0 0
22 23 24 25
0 0 0 0
Description
DocID027809 Rev 4
10 11 12 13
0 0 0 0
26 27 28 29
EFAI
0 0 0 0
RM0400
Access: RW
14 15
0 0
30 31
0 0