Start Of Conversion Pulse Delay - STMicroelectronics SPC572L series Reference Manual

Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface
Table 416. TCDR96–TCDR127 field descriptions(Continued)
Field
Data overwritten flag
This bit signals that the previous converted data has been overwritten by a new conversion. This
functionality depends on the value of MCR[OWREN]:
13 – When OWREN = 0, OVERW is frozen to 0 and CDATA field is protected against being
overwritten until being read.
OVERW
– When OWREN = 1, OVERW flags the CDATA field overwrite status.
0 Converted data has not been overwritten
1 Previous converted data has been overwritten before having been read
Conversion result mode status
This bit reflects the mode of conversion for the corresponding channel.
14–15
00 Data is a result of Normal conversion mode
RESULT[1:0]
01 Data is a result of Injected conversion mode
10 Data is a result of CTU conversion mode
11 Reserved
Channel converted data
Note: If MCR[WLSIDE] is set to '0' than the converted data is read right aligned with lower 12/10
bits representing the actual converted data(width of actual converted data depends on selected
resolution of current conversion, selectable by CTRx[CRES] bit) and remaining upper 4/6 bits
16–31
are read as zeros.
CDATA
Whereas if the MCR[WLSIDE] is set as '1' than the converted data is read left aligned with upper
12/10 bits representing the actual converted data(width of actual converted data depends on
selected resolution of current conversion, selectable by CTRx[CRES] bit) and remaining lower
4/6 bits are read as zeros.
The length of the useful converted data out of 16 bits of CDATA field also depends on the
generic resolution and conv_mode_select. Each of TCDRx corresponds to a test channel
inferred through generic num_testch and if any of the num_testch(i) is '0', the corresponding
TCDRx is not implemented and any access to it generates a transfer error.
These registers are accessed 32-bit R/W.
The REFSEL bit implementation is dependent on parameter vector altref_exists_ch[127:96].
36.6

Start of conversion pulse delay

The following table lists delays between various trigger points (initiation request for
conversion as registered at system clock) and actual issue of start pulse (adc_start) to the
ADC hardmacrocell. Here each possible trigger source is described with the number of
clock cycles required for different operations until trigger of adc_start. This table do not take
into account any software delay involved in programming or polling of any bit in order to
measure conversion timing.
800/2058
Description
DocID027809 Rev 4