STMicroelectronics SPC572L series Reference Manual page 639

RM0400
} while ( !(tmp & 0x0000_0400) );
Note that there is no need to clear MCR[EHV] and MCR[ERS] in order to perform reads
during Erase-Suspend.
The Erase sequence is resumed by writing a logic '0' to MCR[ESUS].
MCR[EHV] must be set to '1' before MCR[ESUS] can be cleared to resume the operation.
The module continues the Erase sequence from one of a set of predefined points and this
may extend the time required for the Erase operation.
MCR= 0x0000_0005;/* Reset ESUS in MCR: Erase Resume */
Repeated suspends at a high frequency may result in the operation timing out and the
embedded flash memory responds by completing the operation with a fail code
(MCR[PEG]=0). The minimum time between Erase suspends to ensure this does not occur
is t .
ESRT
29.4.5.5.2 Factory Erase
The Factory Erase feature can be used only once through a diary location mechanism. If
location UTEST at offset +0x0020 was virgin at the moment of the reset, MCR[FERS] can
be set after rising MCR[ERS] and before MCR[EHV]. After setting MCR[EHV] the FPEC
recognizes the value of FERS and checks if the diary location has been programmed by the
user (having changed from being virgin at reset). Under those conditions a factory Erase
can commence and no Read-While-Write is allowed (all the f90_busy sideband signals are
set high).
29.4.5.6 User Test mode
Customers can put the Flash Memory module in User Test mode to perform specific tests
for the integrity of the flash array.
Two kinds of test can be performed:
•
Array Integrity Self Check
• Margin Read
User Test mode is an exclusive operation—it cannot be run in conjunction with any other
flash mode (Read, Write, Low-Power and Power-Down), and Read-While-Write functionality
is inapplicable. Read accesses attempted by the user during User Test mode generates a
Read-While-Write Error (RWE of MCR set).
It is not permitted to perform User Test operations on the Test blocks (including the UTEST
section).
29.4.5.6.1 Array Integrity Self Check
Array integrity is checked using a predefined address sequence (proprietary), and this
operation is executed on selected (SEL0, SEL1 and SEL2) blocks. Blocks marked by
TMDBS are automatically excluded from MISR signature computation. Any random or non-
random code is valid. Once the operation is completed, the results of the reads can be
checked by reading the MISR value (stored in UM0–9), to determine if an incorrect Read, or
ECC detection was noted. Array integrity is controlled by the pfb clock (fclk) and requires
that the Read Wait States and Address Pipelined control registers in the BIU be set to match
the frequency being used.
Example 9. Block Erase Resume.
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Embedded Flash Memory (MP55)
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