STMicroelectronics ST72361 Auto Series Manual
STMicroelectronics ST72361 Auto Series Manual

STMicroelectronics ST72361 Auto Series Manual

8-bit mcu for automotive with flash or rom, 10-bit adc, 5 timers, spi, linsci
Table of Contents

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Features
Memories
– 16 K to 60 K High Density Flash (HDFlash)
or ROM with read-out protection capability.
In-application programming and in-circuit
programming for HDFlash devices
– 1.5 to 2 K RAM
– HDFlash endurance: 100 cycles, data
retention 20 years at 55 °C
Clock, reset and supply management
– Low power crystal/ceramic resonator
oscillators and bypass for external clock
– PLL for 2 x frequency multiplication
– 5 power saving modes: halt, auto wake up
from halt, active halt, wait and slow
Interrupt management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– TLI top level interrupt (on 64-pin devices)
– Up to 21 external interrupt lines (on 4
vectors)
Up to 48 I/O ports
– Up to 48 multifunctional bidirectional I/O
lines
– Up to 36 alternate function lines
– Up to 6 high sink outputs
5 timers
– 16-bit timer with 2 input captures, 2 output
compares, external clock input, PWM and
pulse generator modes
– 8-bit timer with 1 or 2 input captures, 1 or 2
output compares, PWM and pulse
generator modes
– 8-bit PWM auto-reload timer with 1 or 2
input captures, 2 or 4 independent PWM
output channels, output compare and time
base interrupt, external clock with event
detector
August 2010
8-bit MCU for automotive with Flash or ROM,
10-bit ADC, 5 timers, SPI, LINSCI™
Table 1.
Reference
ST72361xx
Doc ID 12468 Rev 3
ST72361xx-Auto
LQFP32 7x7mm
LQFP44 10x10mm
– Main clock controller with real-time base
and clock output
– Window watchdog timer
Up to 3 communications interfaces
– SPI synchronous serial interface
– Master/ slave LINSCI™ asynchronous
serial interface
– Master only LINSCI™ asynchronous serial
interface
Analog peripheral (low current coupling)
– 10-bit A/D converter with up to 16 inputs
– Up to 9 robust ports (low current coupling)
Instruction set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
Development tools
– Full hardware/ software development
package
Device summary
ST72361K4-Auto, ST72361K6-Auto,
ST72361K7-Auto, ST72361K9-Auto,
ST72361J4-Auto, ST72361J6-Auto,
-Auto
ST72361J7-Auto, ST72361J9-Auto,
ST72361AR4-Auto, ST72361AR6-Auto,
ST72361AR7-Auto, ST72361AR9-Auto
LQFP64 10x10mm
Part number
1/279
www.st.com
1

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Summary of Contents for STMicroelectronics ST72361 Auto Series

  • Page 1: Table 1. Device Summary

    ST72361xx-Auto 8-bit MCU for automotive with Flash or ROM, 10-bit ADC, 5 timers, SPI, LINSCI™ Features ■ Memories – 16 K to 60 K High Density Flash (HDFlash) LQFP32 7x7mm or ROM with read-out protection capability. In-application programming and in-circuit programming for HDFlash devices –...
  • Page 2: Table Of Contents

    Contents ST72361xx-Auto Contents Description ..........19 Pin description .
  • Page 3 ST72361xx-Auto Contents 5.5.2 Asynchronous external RESET pin ......42 5.5.3 External power-on reset ........42 5.5.4 Internal low voltage detector (LVD) reset .
  • Page 4 Contents ST72361xx-Auto 8.2.2 Output modes ..........72 8.2.3 Alternate functions .
  • Page 5 ST72361xx-Auto Contents 11.2 Functional description ........92 11.2.1 Counter .
  • Page 6 Contents ST72361xx-Auto 12.7.8 Output compare 2 high register (OC2HR) ..... . 120 12.7.9 Output compare 2 low register (OC2LR) ..... . . 121 12.7.10 Counter high register (CHR) .
  • Page 7 ST72361xx-Auto Contents 14.2 Main features ..........143 14.3 General description .
  • Page 8 Contents ST72361xx-Auto 15.8 SCI mode register description ....... . 167 15.8.1 Status register (SCISR) .
  • Page 9 ST72361xx-Auto Contents 16.4.2 Transmitter ..........196 16.4.3 Receiver .
  • Page 10 Contents ST72361xx-Auto 18.1.1 Inherent ..........220 18.1.2 Immediate .
  • Page 11 ST72361xx-Auto Contents 19.8.1 Functional EMS (electromagnetic susceptibility) ....238 19.8.2 Electromagnetic interference (EMI) ......239 19.8.3 Absolute maximum ratings (electrical sensitivity) .
  • Page 12 Contents ST72361xx-Auto 23.2 Flash/FastROM devices only ....... . . 273 23.2.1 LINSCI wrong break duration .
  • Page 13 ST72361xx-Auto List of tables List of tables Table 1. Device summary ............1 Table 2.
  • Page 14 List of tables ST72361xx-Auto Table 49. Timer modes ............116 Table 50.
  • Page 15 ST72361xx-Auto List of tables Table 101. EMS test results ............239 Table 102.
  • Page 16 List of figures ST72361xx-Auto List of figures Figure 1. Device block diagram ........... . . 20 Figure 2.
  • Page 17 ST72361xx-Auto List of figures Figure 49. Counter timing diagram, internal clock divided by 2 ......106 Figure 50.
  • Page 18 List of figures ST72361xx-Auto Figure 101. PLL jitter vs signal frequency ..........236 Figure 102.
  • Page 19: Description

    ST72361xx-Auto Description Description The ST72361xx-Auto devices are members of the ST7 microcontroller family designed for automotive mid-range applications with LIN (Local Interconnect Network) interface. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code.
  • Page 20: Figure 1. Device Block Diagram

    Description ST72361xx-Auto Figure 1. Device block diagram option OSC1 PLL x 2 OSC2 8-Bit TIMER 16-Bit TIMER PA7:0 PORT A POWER (8 bits) SUPPLY PB7:0 PORT B (8 bits) PC7:0 PORT C (8 bits) RESET PD7:0 PORT D CONTROL (8 bits) PE7:0 PORT E 8-BIT CORE...
  • Page 21: Pin Description

    ST72361xx-Auto Description Pin description Figure 2. LQFP 64-pin package pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PD2 / LINSCI1_TDO OSC1 PD1 / LINSCI1_RDI OSC2 PF2 / AIN8 ARTIC1 / PA0 PF1 / AIN7 PWM0 / PA1 PWM1 / (HS) PA2...
  • Page 22: Figure 3. Lqfp 44-Pin Package Pinout

    Description ST72361xx-Auto Figure 3. LQFP 44-pin package pinout 44 43 42 41 40 39 38 37 36 35 34 OSC1 PD2 / LINSCI1_TDO OSC2 PD1 / LINSCI1_RDI PWM0 / PA1 PF2 / AIN8 PF1 / AIN7 PWM1 / (HS) PA2 PWM2 / PA3 PD0 / SPI_SS / AIN6 PWM3 / PA4...
  • Page 23: Figure 4. Lqfp 32-Pin Package Pinout

    ST72361xx-Auto Description Figure 4. LQFP 32-pin package pinout 32 31 30 29 28 27 26 25 OSC1 PD2 / LINSCI1_TDO OSC2 PD1 / LINSCI1_RDI PWM0 / PA1 PD0 / SPI_SS / AIN6 PWM1 / (HS) PA2 PC7 / SPI_SCK ARTCLK / (HS) PA5 PC6 / SPI_MOSI T8_OCMP1 / PB1 PC5 / SPI_MISO...
  • Page 24: Table 3. Device Pin Description

    Description ST72361xx-Auto List of abbreviations used in Table 3 Type: I = input, O = output, S = supply In/Output level: C = CMOS 0.3V /0.7V with Schmitt trigger = TTL 0.8V / 2V with Schmitt trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog,...
  • Page 25 ST72361xx-Auto Description Table 3. Device pin description (continued) Pin n° Level Port Main function Input Output Pin name Alternate function (after reset) PE2 / AIN14 I/O T RB X Port E2 ADC analog input 14 PE3 / AIN15 I/O T RB X Port E3 ADC analog input 15 ICC data...
  • Page 26 Description ST72361xx-Auto Table 3. Device pin description (continued) Pin n° Level Port Main function Input Output Pin name Alternate function (after reset) I/O T Port F0 45 30 PF1 / AIN7 I/O T Port F1 ADC analog input 7 46 31 PF2 / AIN8 I/O T Port F2...
  • Page 27: Register And Memory Map

    ST72361xx-Auto Register and memory map Register and memory map As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of RAM and up to 60 Kbytes of user program memory.
  • Page 28 Register and memory map ST72361xx-Auto Table 4. Hardware register map (continued) Register Reset Address Block Register name Remarks label status 000Fh PFDR Port F Data Register 0010h Port F PFDDR Port F Data Direction Register 0011h PFOR Port F Option Register 0012h Reserved Area (15 bytes) 0020h...
  • Page 29 ST72361xx-Auto Register and memory map Table 4. Hardware register map (continued) Register Reset Address Block Register name Remarks label status 0048h SCI1ISR SCI1 Status Register Read Only 0049h SCI1DR SCI1 Data Register 004Ah SCI1BRR SCI1 Baud Rate Register LINSCI1 004Bh SCI1CR1 SCI1 Control Register 1 (LIN...
  • Page 30: Flash Program Memory

    Flash program memory ST72361xx-Auto Flash program memory Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by- Byte basis using an external V supply.
  • Page 31: Read-Out Protection

    ST72361xx-Auto Flash program memory 3.3.1 Read-out protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.
  • Page 32: Icp (In-Circuit Programming)

    (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware...
  • Page 33: Iap (In-Application Programming)

    ST72361xx-Auto Flash program memory interface on the application board (see Figure 7). For more details on the pin locations, refer to the device pinout description. IAP (in-application programming) This mode uses a Bootloader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).
  • Page 34: Central Processing Unit

    Central processing unit ST72361xx-Auto Central processing unit Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. Main features ● Enable executing 63 basic instructions ● Fast 8-bit by 8-bit multiply ● 17 main addressing modes (with indirect addressing mode) ●...
  • Page 35: Condition Code Register (Cc)

    ST72361xx-Auto Central processing unit Figure 8. CPU registers ACCUMULATOR RESET VALUE = XXh X INDEX REGISTER RESET VALUE = XXh Y INDEX REGISTER RESET VALUE = XXh PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 1 I1 H I0 N Z CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X...
  • Page 36: Table 7. Interrupt Software Priority Selection

    Central processing unit ST72361xx-Auto This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero.
  • Page 37: Stack Pointer (Sp)

    ST72361xx-Auto Central processing unit 4.3.5 Stack pointer (SP) Read/ write Reset value: 01 FFh The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
  • Page 38: Figure 9. Stack Manipulation Example

    Central processing unit ST72361xx-Auto Figure 9. Stack manipulation example CALL PUSH Y POP Y IRET Interrupt Subroutine or RSP Event @ 0100h @ 01FFh Stack Higher Address = 01FFh Stack Lower Address = 0100h 38/279 Doc ID 12468 Rev 3...
  • Page 39: Supply, Reset And Clock Management

    ST72361xx-Auto Supply, reset and clock management Supply, reset and clock management Introduction The device includes a range of utility features for securing the application in critical situations (for example, in case of a power brown-out), and reducing the number of external components.
  • Page 40: Multi-Oscillator (Mo)

    Supply, reset and clock management ST72361xx-Auto Figure 11. Clock, reset and supply block diagram / 8000 8-BIT TIMER MAIN CLOCK MULTI- OSC2 OSC2 CONTROLLER OSCILLATOR WITH REALTIME (option) OSC1 CLOCK (MCC/RTC) (MO) SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE WATCHDOG AVD Interrupt Request RESET MANAGER TIMER (WDG)
  • Page 41: Reset Sequence Manager (Rsm)

    ST72361xx-Auto Supply, reset and clock management output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Table 8.
  • Page 42: Asynchronous External Reset Pin

    Supply, reset and clock management ST72361xx-Auto The reset vector fetch phase duration is two clock cycles. Figure 12. RESET sequence phases RESET INTERNAL RESET FETCH Active Phase 256 or 4096 CLOCK CYCLES VECTOR 5.5.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor.
  • Page 43: Internal Watchdog Reset

    ST72361xx-Auto Supply, reset and clock management The device RESET pin acts as an output that is pulled low when V < V (rising edge) or < V (falling edge) as shown in Figure The LVD filters spikes on V larger than t to avoid parasitic resets.
  • Page 44: Auxiliary Voltage Detector (Avd)

    Supply, reset and clock management ST72361xx-Auto The LVD function is illustrated in Figure Provided the minimum V value (guaranteed for the oscillator frequency) is above V IT-(LVD) the MCU can only be in two modes: ● under full software control ●...
  • Page 45: Low Power Modes

    ST72361xx-Auto Supply, reset and clock management If t is greater than 256 or 4096 cycles then: ● If the AVD interrupt is enabled before the V threshold is reached, then two AVD IT+(AVD) interrupts will be received: The first when the AVDIE bit is set and the second when the threshold is reached.
  • Page 46: Register Description

    Supply, reset and clock management ST72361xx-Auto 5.6.5 Register description System integrity (SI) control/status register (SICSR) Read/Write Reset value: 000x 000x (00h) AVDIE AVDF LVDRF WDGRF Bit 7 = Reserved, must be kept cleared. Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software.
  • Page 47: Table 11. Reset Source Flags

    ST72361xx-Auto Supply, reset and clock management Table 11. Reset source flags RESET sources LVDRF WDGRF External RESET pin Watchdog Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
  • Page 48: Interrupts

    Interrupts ST72361xx-Auto Interrupts Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – Up to 4 software programmable nesting levels –...
  • Page 49: Table 12. Interrupt Software Priority Levels

    ST72361xx-Auto Interrupts Table 12. Interrupt software priority levels Interrupt software priority Level Level 0 (main) Level 1 Level 2 High Level 3 (= interrupt disable) Figure 17. Interrupt processing flowchart PENDING RESET INTERRUPT Interrupt has the same or a lower software priority than current one I1:0 FETCH NEXT...
  • Page 50 Interrupts ST72361xx-Auto When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt.
  • Page 51: Interrupts And Low Power Modes

    ST72361xx-Auto Interrupts if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch.
  • Page 52: Interrupt Register Description

    Interrupts ST72361xx-Auto Figure 20. Nested interrupt management SOFTWARE PRIORITY LEVEL MAIN MAIN 11 / 10 Interrupt register description 6.5.1 CPU CC register interrupt bits Read/Write Reset value: 111x 1010 (xAh) Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority. Table 13.
  • Page 53: Interrupt Software Priority Registers (Isprx)

    ST72361xx-Auto Interrupts 6.5.2 Interrupt software priority registers (ISPRX) Read/ write (bit 7:4 of ISPR3 are read only) Reset value: 1111 1111 (FFh) ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0 ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4 ISPR2 I1_11 I0_11...
  • Page 54 Interrupts ST72361xx-Auto Table 15. Dedicated interrupt instruction set (continued) Instruction New description Function/example POP CC Pop CC from the Stack Mem => CC Enable interrupt (level 0 set) Load 10 in I1:0 of CC Disable interrupt (level 3 set) Load 11 in I1:0 of CC TRAP Software trap Software NMI...
  • Page 55: Table 16. Interrupt Mapping

    ST72361xx-Auto Interrupts Table 16. Interrupt mapping Exit Source Register Priority Address N° Description from block label order vector Halt FFFEh- RESET Reset FFFFh FFFCh- TRAP Software interrupt FFFDh FFFAh- External top level interrupt EICR FFFBh MCC/RTC Main clock controller time base interrupt MCCSR FFF8h-FFF9h EICR/AW...
  • Page 56: External Interrupts

    Interrupts ST72361xx-Auto External interrupts 6.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the ISxx bits in the EICR register (Figure 21). This control allows up to four fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: ●...
  • Page 57: Figure 21. External Interrupt Control Bits

    ST72361xx-Auto Interrupts Figure 21. External interrupt control bits EICR PORT A [7:0] INTERRUPTS IS00 IS01 PAOR.0 PADDR.0 SENSITIVITY CONTROL ei0 INTERRUPT SOURCE AWUFH EICR PORT B [5:0] INTERRUPTS / AWUPR Oscillator IS10 IS11 To Timer Input Capture 1 PBOR.0 PBDDR.0 SENSITIVITY CONTROL ei1 INTERRUPT SOURCE...
  • Page 58: Register Description

    Interrupts ST72361xx-Auto 6.6.2 Register description External interrupt control register 0 (EICR0) Read/Write Reset value: 0000 0000 (00h) IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00 Bits 7:6 = IS3[1:0] ei3 sensitivity The interrupt sensitivity, defined using the IS3[1:0] bits, is applied to the ei3 external interrupts: Table 17.
  • Page 59: Table 20. Interrupt Sensitivity - Ei0

    ST72361xx-Auto Interrupts Table 19. Interrupt sensitivity - ei1 IS11 IS10 External interrupt sensitivity Falling edge only Rising and falling edge These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bits 1:0 = IS0[1:0] ei0 sensitivity The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts:...
  • Page 60: Table 21. Nested Interrupts Register Map And Reset Values

    Interrupts ST72361xx-Auto Table 21. Nested interrupts register map and reset values Address Register (Hex.) label CLKM 0025h ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 Reset value 0026h ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4 Reset value LINSCI 2 TIMER 16 TIMER 8 0027h...
  • Page 61: Power Saving Modes

    ST72361xx-Auto Power saving modes Power saving modes Introduction To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see Figure 22): ● Slow ● Wait (and Slow-Wait) ●...
  • Page 62: Wait Mode

    Power saving modes ST72361xx-Auto In this mode, the master clock frequency (f ) can be divided by 2, 4, 8 or 16. The CPU OSC2 and peripherals are clocked at this lower frequency (f Note: SLOW-WAIT mode is activated by entering WAIT mode while the device is in SLOW mode. Figure 23.
  • Page 63: Halt Mode

    ST72361xx-Auto Power saving modes Figure 24. WAIT mode flow-chart OSCILLATOR PERIPHERALS WFI INSTRUCTION I[1:0] BITS RESET INTERRUPT OSCILLATOR PERIPHERALS I[1:0] BITS 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS I[1:0] BITS FETCH RESET VECTOR OR SERVICE INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
  • Page 64: Figure 25. Halt Timing Overview

    Power saving modes ST72361xx-Auto system is enabled, can generate a Watchdog RESET (see Section 22.1: Introduction more details). Figure 25. HALT timing overview 256 OR 4096 CPU HALT CYCLE DELAY RESET INTERRUPT HALT INSTRUCTION FETCH [MCCSR.OIE=0] VECTOR Figure 26. HALT mode flow-chart HALT INSTRUCTION (MCCSR.OIE=0) (AWUCSR.AWUEN=0)
  • Page 65: Active Halt Mode

    ST72361xx-Auto Power saving modes Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction.
  • Page 66: Auto Wake-Up From Halt Mode

    Power saving modes ST72361xx-Auto Note: As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.
  • Page 67: Figure 29. Awufh Mode Block Diagram

    ST72361xx-Auto Power saving modes It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set and the OIE bit in the MCCSR register is cleared (see Section 10: Main clock controller with real time clock MCC/RTC for more details).
  • Page 68: Figure 30. Awuf Halt Timing Diagram

    Power saving modes ST72361xx-Auto Figure 30. AWUF halt timing diagram RUN MODE HALT MODE 256 or 4096 t RUN MODE AWU_RC Clear by software AWUFH interrupt Figure 31. AWUFH mode flow-chart HALT INSTRUCTION (MCCSR.OIE=0) (AWUCSR.AWUEN=1) ENABLE WATCHDOG DISABLE WDGHALT AWU RC OSC WATCHDOG MAIN OSC RESET...
  • Page 69: Register Description

    ST72361xx-Auto Power saving modes 7.6.1 Register description AWUFH control/status register (AWUCSR) Read/Write (except bit 2 read only) Reset value: 0000 0000 (00h) AWUF AWUM AWUEN Bits 7:3 = Reserved. Bit 2 = AWUF Auto Wake-Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR.
  • Page 70: Table 24. Awu Register Map And Reset Values

    Power saving modes ST72361xx-Auto Table 23. AWUPR prescaler (continued) AWUPR[7:0 Dividing factor In AWU mode, the period that the MCU stays in Halt Mode (t Figure 30) is defined by   AWUP --------------------- - RCSTRT AWURC This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically.
  • Page 71: I/O Ports

    ST72361xx-Auto I/O ports I/O ports Introduction The I/O ports offer different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.
  • Page 72: Output Modes

    I/O ports ST72361xx-Auto Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed.
  • Page 73: Table 26. I/O Port Mode Options

    ST72361xx-Auto I/O ports Figure 32. I/O port general block diagram ALTERNATE REGISTER OUTPUT P-BUFFER ACCESS (see table below) ALTERNATE PULL-UP ENABLE (see table below) PULL-UP CONDITION If implemented OR SEL N-BUFFER DIODES (see table below) DDR SEL ANALOG INPUT CMOS SCHMITT DR SEL TRIGGER...
  • Page 74: Table 27. I/O Port Configurations

    I/O ports ST72361xx-Auto Table 27. I/O port configurations Hardware configuration NOT IMPLEMENTED IN DR REGISTER ACCESS TRUE OPEN DRAIN I/O PORTS PULL-UP CONDITION REGISTER DATA BUS ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE ( INTERRUPT CONDITION ANALOG INPUT NOT IMPLEMENTED IN DR REGISTER ACCESS TRUE OPEN DRAIN I/O PORTS DATA BUS...
  • Page 75: I/O Port Implementation

    ST72361xx-Auto I/O ports Warning: The analog input voltage level must be within the limits stated in the absolute maximum ratings. I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects.
  • Page 76: Interrupt Ports

    I/O ports ST72361xx-Auto 8.4.2 Interrupt ports Table 29. Configuration of PA0, 2, 4, 6; PB0, 2,4; PC1; PD0,6 (with pull-up) Mode Floating input Pull-up interrupt input Open drain output Push-pull output Table 30. Configuration of PA1, 3, 5, 7; PB1,3,5; PC2; PD1, 4, 7 (without pull-up) Mode Floating input Floating interrupt input...
  • Page 77: Pull-Up Input Port

    ST72361xx-Auto I/O ports 8.4.3 Pull-up input port Table 31. Configuration of PC4 Mode pull-up input The PC4 port cannot operate as a general purpose output. If DDR = 1 it is still possible to read the port through the DR register. Table 32.
  • Page 78: Low Power Modes

    I/O ports ST72361xx-Auto Table 32. Port configuration (continued) Input Output Port Pin name OR = 0 OR = 1 OR = 0 OR = 1 pull-up interrupt (ei3) floating interrupt (ei3) PD3:2 pull-up Port D floating floating interrupt (ei3) open drain push-pull pull-up pull-up interrupt (ei3)
  • Page 79: Table 35. I/O Port Register Map And Reset Values

    ST72361xx-Auto I/O ports Table 35. I/O port register map and reset values Address Register (Hex.) label Reset value of all IO port registers 0000h PADR 0001h PADDR 0002h PAOR 0003h PBDR 0004h PBDDR 0005h PBOR 0006h PCDR 0007h PCDDR 0008h PCOR 0009h PDDR...
  • Page 80: Window Watchdog (Wwdg)

    Window watchdog (WWDG) ST72361xx-Auto Window watchdog (WWDG) Introduction The Window Watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared.
  • Page 81: Figure 34. Watchdog Block Diagram

    ST72361xx-Auto Window watchdog (WWDG) Figure 34. Watchdog block diagram WATCHDOG WINDOW REGISTER (WDGWR) RESET comparator = 1 when T6:0 > W6:0 CMP Write WDGCR WATCHDOG CONTROL REGISTER (WDGCR) WDGA 6-BIT DOWNCOUNTER (CNT) MCC/RTC OSC2 DIV 64 WDG PRESCALER DIV 4 12-BIT MCC RTC COUNTER TB[1:0] bits...
  • Page 82: Using Halt Mode With The Wdg

    Window watchdog (WWDG) ST72361xx-Auto Using halt mode with the WDG If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. How to program the watchdog timeout Figure 35 shows the linear relationship between the 6-bit value to be loaded in the...
  • Page 83: Figure 36. Exact Timeout Duration (Tmin And Tmax)

    ST72361xx-Auto Window watchdog (WWDG) Figure 36. Exact timeout duration (t and t WHERE: = (LSB + 128) x 64 x t min0 OSC2 = 16384 x t max0 OSC2 = 125ns if f = 8 MHz OSC2 OSC2 CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register TB1 Bit...
  • Page 84: Low Power Modes

    Window watchdog (WWDG) ST72361xx-Auto Figure 37. Window watchdog timing diagram T[5:0] CNT downcounter WDGWR time (step = 16384/f Refresh not allowed Refresh Window OSC2 T6 bit Reset Low power modes Table 36. Effect of low power modes on WDG Mode Description SLOW No effect on Watchdog: the downcounter continues to decrement at normal speed.
  • Page 85: Using Halt Mode With The Wdg (Wdghalt Option)

    ST72361xx-Auto Window watchdog (WWDG) Using halt mode with the WDG (WDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled. ● Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. Interrupts None.
  • Page 86: Table 37. Watchdog Timer Register Map And Reset Values

    Window watchdog (WWDG) ST72361xx-Auto Table 37. Watchdog timer register map and reset values Address Register label (Hex.) WDGCR WDGA Reset value WDGWR Reset value 86/279 Doc ID 12468 Rev 3...
  • Page 87: Main Clock Controller With Real Time Clock Mcc/Rtc

    ST72361xx-Auto Main clock controller with real time clock MCC/RTC Main clock controller with real time clock MCC/RTC The Main Clock Controller consists of three different functions: ● a programmable CPU clock prescaler ● a clock-out signal to supply external devices ●...
  • Page 88: Low Power Modes

    Main clock controller with real time clock MCC/RTC ST72361xx-Auto 10.4 Low power modes Table 38. Effect of low power modes on MCC/RTC Mode Description No effect on MCC/RTC peripheral. WAIT MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
  • Page 89: Table 40. Cpu Clock Frequency In Slow Mode

    ST72361xx-Auto Main clock controller with real time clock MCC/RTC Table 40. CPU clock frequency in SLOW mode in SLOW mode OSC2 OSC2 OSC2 / 16 OSC2 Bit 4 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode.
  • Page 90: Table 42. Main Clock Controller Register Map And Reset Values

    Main clock controller with real time clock MCC/RTC ST72361xx-Auto Caution: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. Table 42. Main clock controller register map and reset values Address Register (Hex.)
  • Page 91: Pwm Auto-Reload Timer (Art)

    ST72361xx-Auto PWM auto-reload timer (ART) PWM auto-reload timer (ART) 11.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto- reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: ●...
  • Page 92: Functional Description

    PWM auto-reload timer (ART) ST72361xx-Auto 11.2 Functional description 11.2.1 Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR).
  • Page 93: Independent Pwm Signal Generation

    ST72361xx-Auto PWM auto-reload timer (ART) Figure 40. Output compare control COUNTER ARTARR=FDh COUNTER OCRx PWMDCRx PWMx 11.2.5 Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode.
  • Page 94: Output Compare And Time Base Interrupt

    PWM auto-reload timer (ART) ST72361xx-Auto Figure 42. PWM signal from 0% to 100% duty cycle COUNTER ARTARR = FDh COUNTER OCRx=FCh OCRx=FDh OCRx=FEh OCRx=FFh 11.2.6 Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set.
  • Page 95: Figure 44. Input Capture Timing Diagram, Fcounter = Fcpu

    ST72361xx-Auto PWM auto-reload timer (ART) Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status register (ARTICCSR). These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register. The active transition (falling or rising edge) is software programmable through the CSx bits of the ARTICCSR register.
  • Page 96: External Interrupt Capability

    PWM auto-reload timer (ART) ST72361xx-Auto Figure 45. Input capture timing diagram, f COUNTER COUNTER COUNTER ARTICx PIN INTERRUPT ICAP SAMPLED CFx FLAG ICRx REGISTER COUNTER COUNTER INTERRUPT ARTICx PIN ICAP SAMPLED CFx FLAG ICRx REGISTER 11.2.9 External interrupt capability This mode allows the Input capture capabilities to be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx signal.
  • Page 97: Register Description

    ST72361xx-Auto PWM auto-reload timer (ART) 11.3 Register description Control/status register (ARTCSR) Read/Write Reset value: 0000 0000 (00h) EXCL FCRL Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock.
  • Page 98: Table 44. Pwm Frequency Vs Resolution

    PWM auto-reload timer (ART) ST72361xx-Auto Bit 0 = OVF Overflow Flag This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value 0: New transition not yet reached 1: Transition reached Counter Access Register (ARTCAR) Read/Write...
  • Page 99: Table 45. Pwmx Output Level And Polarity

    ST72361xx-Auto PWM auto-reload timer (ART) PWM control register (PWMCR) Read/write Reset value: 0000 0000 (00h) Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0: PWM output disabled.
  • Page 100: Table 46. Pwm Auto-Reload Timer Register Map And Reset Values

    PWM auto-reload timer (ART) ST72361xx-Auto CIE2 CIE1 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture channel. 0: Falling edge triggers capture on channel x.
  • Page 101 ST72361xx-Auto PWM auto-reload timer (ART) Table 46. PWM auto-reload timer register map and reset values (continued) Address Register label (Hex.) PWMCR 0035h Reset value ARTCSR EXCL FCRL 0036h Reset value ARTCAR 0037h Reset value ARTARR 0038h Reset value ARTICCSR 0039h Reset value ARTICR1 003Ah...
  • Page 102: 16-Bit Timer

    16-bit timer ST72361xx-Auto 16-bit timer 12.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).
  • Page 103: Functional Description

    ST72361xx-Auto 16-bit timer 12.3 Functional description 12.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter Register (CR): ●...
  • Page 104: Figure 47. Timer Block Diagram

    16-bit timer ST72361xx-Auto Figure 47. Timer block diagram ST7 INTERNAL BUS MCU-PERIPHERAL INTERFACE 8 low 8 high 8-bit buffer EXEDG INPUT OUTPUT INPUT OUTPUT COUNTER CAPTURE COMPARE COMPARE CAPTURE REGISTER REGISTER REGISTER REGISTER REGISTER ALTERNATE EXTCLK COUNTER REGISTER CC[1:0] TIMER INTERNAL BUS OVERFLOW EDGE DETECT OUTPUT COMPARE...
  • Page 105: External Clock

    ST72361xx-Auto 16-bit timer The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read.
  • Page 106: Input Capture

    16-bit timer ST72361xx-Auto Figure 49. Counter timing diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK FFFD FFFE FFFF 0000 0001 0002 0003 COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 50. Counter timing diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK...
  • Page 107: Procedure

    ST72361xx-Auto 16-bit timer The active transition is software programmable through the IEDGi bit in the control register (CRi). Timing resolution is one count of the free running counter: ( CC[1:0]). 12.3.4 Procedure To use the input capture function select the following in the CR2 register: ●...
  • Page 108: Output Compare

    16-bit timer ST72361xx-Auto Figure 52. Input capture block diagram ICAP1 (Control Register 1) CR1 EDGE DETECT EDGE DETECT ICIE IEDG1 CIRCUIT2 CIRCUIT1 ICAP2 (Status Register) SR IC2R Register IC1R Register ICF1 ICF2 (Control Register 2) CR2 16-BIT 16-BIT FREE RUNNING IEDG2 COUNTER Figure 53.
  • Page 109: Procedure

    ST72361xx-Auto 16-bit timer These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC R value to 8000h. Timing resolution is one count of the free running counter: ( CPU/ CC[1:0] 12.3.6 Procedure To use the output compare function, select the following in the CR2 register:...
  • Page 110: Forced Compare Output Capability

    16-bit timer ST72361xx-Auto The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OC R register: ● Write to the OCiHR register (further compares are inhibited). ●...
  • Page 111: One Pulse Mode

    ST72361xx-Auto 16-bit timer Figure 55. Output compare timing diagram, f TIMER INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 OUTPUT COMPARE REGISTER i (OCRi) 2ED3 OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 56.
  • Page 112 16-bit timer ST72361xx-Auto Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 50).
  • Page 113: Pulse Width Modulation Mode

    ST72361xx-Auto 16-bit timer Note: The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.
  • Page 114 16-bit timer ST72361xx-Auto Procedure To use Pulse Width Modulation mode: Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.
  • Page 115: Low Power Modes

    ST72361xx-Auto 16-bit timer External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure Note: After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written.
  • Page 116: Summary Of Timer Modes

    16-bit timer ST72361xx-Auto Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 12.6 Summary of timer modes Table 49.
  • Page 117: Control Register 2 (Cr2)

    ST72361xx-Auto 16-bit timer Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin.
  • Page 118: Control/Status Register (Csr)

    16-bit timer ST72361xx-Auto Bit 5 = OPM One Pulse Mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
  • Page 119: Input Capture 1 High Register (Ic1Hr)

    ST72361xx-Auto 16-bit timer Bit 6 = OCF1 Output Compare Flag 1. 0: nomatch (reset value). 1: the content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.
  • Page 120: Input Capture 1 Low Register (Ic1Lr)

    16-bit timer ST72361xx-Auto 12.7.5 Input capture 1 low register (IC1LR) Read only Reset value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 12.7.6 Output compare 1 high register (OC1HR) Read/ write Reset value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR...
  • Page 121: Output Compare 2 Low Register (Oc2Lr)

    ST72361xx-Auto 16-bit timer 12.7.9 Output compare 2 low register (OC2LR) Read/ write Reset value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 12.7.10 Counter high register (CHR) Read only Reset value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
  • Page 122: Alternate Counter Low Register (Aclr)

    16-bit timer ST72361xx-Auto 12.7.13 Alternate counter low register (ACLR) Read only Reset value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register.
  • Page 123: Table 51. 16-Bit Timer Register Map

    ST72361xx-Auto 16-bit timer Table 51. 16-bit timer register map (continued) Address Register name (Hex.) IC1HR IC1LR OC1HR OC1LR ACHR ACLR IC2HR IC2LR OC2HR OC2LR Doc ID 12468 Rev 3 123/279...
  • Page 124: 8-Bit Timer (Tim8)

    8-bit timer (TIM8) ST72361xx-Auto 8-bit timer (TIM8) 13.1 Introduction The timer consists of a 8-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).
  • Page 125 ST72361xx-Auto 8-bit timer (TIM8) Writing in the CTR register or ACTR register resets the free running counter to the FCh value. Both counters have a reset value of FCh (this is the only value which is reloaded in the 8-bit timer).
  • Page 126: Figure 59. Timer Block Diagram

    8-bit timer (TIM8) ST72361xx-Auto Figure 59. Timer block diagram ST7 INTERNAL BUS MCU-PERIPHERAL INTERFACE INPUT INPUT OUTPUT OUTPUT COUNTER CAPTURE CAPTURE COMPARE COMPARE REGISTER REGISTER REGISTER REGISTER REGISTER 1/8000 ALTERNATE OSC2 COUNTER REGISTER CC[1:0] TIMER INTERNAL BUS OVERFLOW EDGE DETECT OUTPUT COMPARE ICAP1 DETECT...
  • Page 127: Figure 60. Counter Timing Diagram, Internal Clock Divided By 2

    ST72361xx-Auto 8-bit timer (TIM8) Reading the SR register while the TOF bit is set. An access (read or write) to the CTR register. Note: The TOF bit is not cleared by accesses to ACTR register. The advantage of accessing the ACTR register rather than the CTR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
  • Page 128: Input Capture

    8-bit timer (TIM8) ST72361xx-Auto 13.3.2 Input capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 8-bit timer. The two 8-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 63).
  • Page 129: Output Compare

    ST72361xx-Auto 8-bit timer (TIM8) Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFh).
  • Page 130 8-bit timer (TIM8) ST72361xx-Auto These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC R value to 00h. Timing resolution is one count of the free running counter: (f CC[1:0] Procedure To use the output compare function, select the following in the CR2 register: ●...
  • Page 131: Forced Compare Output Capability

    ST72361xx-Auto 8-bit timer (TIM8) When the timer clock is f /4, f /8 or f /8000, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 67). The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used.
  • Page 132: One Pulse Mode

    8-bit timer (TIM8) ST72361xx-Auto Figure 67. Output compare timing diagram, f TIMER CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) 13.3.5 One pulse mode One Pulse mode enables the generation of a pulse when an external event occurs.
  • Page 133 ST72361xx-Auto 8-bit timer (TIM8) One pulse mode cycle ICR1 = Counter When OCMP1 = OLVL2 event occurs on ICAP1 Counter is reset to FCh ICF1 bit is set When Counter OCMP1 = OLVL1 = OC1R Then, on a valid event on the ICAP1 pin, the counter is initialized to FCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.
  • Page 134: Pulse Width Modulation Mode

    8-bit timer (TIM8) ST72361xx-Auto Figure 68. One pulse mode timing example IC1R COUNTER ICAP1 OLVL2 OLVL1 OLVL2 OCMP1 compare1 Note: IEDG1 = 1, OC1R = D0h, OLVL1 = 0, OLVL2 = 1 Figure 69. Pulse width modulation mode timing example COUNTER E2 OLVL2 OLVL1...
  • Page 135 ST72361xx-Auto 8-bit timer (TIM8) Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.
  • Page 136: Low Power Modes

    8-bit timer (TIM8) ST72361xx-Auto set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.
  • Page 137: Summary Of Timer Modes

    ST72361xx-Auto 8-bit timer (TIM8) 13.6 Summary of timer modes Table 54. Timer modes Available resources Modes Output compare Input capture 1 Input capture 2 Output compare 2 Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse Mode Partially Recommended PWM Mode...
  • Page 138: Control Register 2 (Cr2)

    8-bit timer (TIM8) ST72361xx-Auto Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison.
  • Page 139: Control/Status Register (Csr)

    ST72361xx-Auto 8-bit timer (TIM8) Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.
  • Page 140: Input Capture 1 Register (Ic1R)

    8-bit timer (TIM8) ST72361xx-Auto Note: Reading or writing the ACTR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the IC2R register.
  • Page 141: Output Compare 2 Register (Oc2R)

    ST72361xx-Auto 8-bit timer (TIM8) 13.7.6 Output compare 2 register (OC2R) Read/ write Reset value: 0000 0000 (00h) This is an 8-bit register that contains the value to be compared to the CTR register. 13.7.7 Counter register (CTR) Read only Reset value: 1111 1100 (FCh) This is an 8-bit register that contains the counter value.
  • Page 142: 8-Bit Timer Register Map

    8-bit timer (TIM8) ST72361xx-Auto 13.8 8-bit timer register map Address Register name (Hex.) OC1E OC2E IEDG2 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 ICF1 OCF1 ICF2 OCF2 TIMD IC1R OC1R ACTR IC2R OC2R 142/279 Doc ID 12468 Rev 3...
  • Page 143: Serial Peripheral Interface (Spi)

    ST72361xx-Auto Serial peripheral interface (SPI) Serial peripheral interface (SPI) 14.1 Introduction The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 14.2 Main features ●...
  • Page 144: Functional Description

    Serial peripheral interface (SPI) ST72361xx-Auto Figure 70. Serial peripheral interface block diagram Data/Address Bus Read SPIDR Interrupt request Read Buffer MOSI SPICSR MISO 8-Bit Shift Register SPIF WCOL MODF Write STATE CONTROL SPICR MSTR SPR0 SPIE SPR2 CPOL CPHA SPR1 MASTER CONTROL SERIAL CLOCK...
  • Page 145: Slave Select Management

    ST72361xx-Auto Serial peripheral interface (SPI) Figure 71. Single master/ single slave application SLAVE MASTER MSBit LSBit MSBit LSBit MISO MISO 8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER MOSI MOSI CLOCK GENERATOR Not used if SS is managed by software 14.3.2 Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software.
  • Page 146: Master Mode Operation

    Serial peripheral interface (SPI) ST72361xx-Auto Figure 73. Hardware/software slave select management SSM bit SSI bit SS internal SS external pin 14.3.3 Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).
  • Page 147: Slave Mode Operation

    ST72361xx-Auto Serial peripheral interface (SPI) 14.3.5 Slave mode operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: Write to the SPICSR register to perform the following actions: –...
  • Page 148: Error Flags

    Serial peripheral interface (SPI) ST72361xx-Auto MISO pin and the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Figure 74.
  • Page 149: Overrun Condition (Ovr)

    ST72361xx-Auto Serial peripheral interface (SPI) Clearing the MODF bit is done through a software sequence: A read access to the SPICSR register while the MODF bit is set. A write to the SPICR register. Note: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence.
  • Page 150: Figure 75. Clearing The Wcol Bit (Write Collision Flag) Software Sequence

    Serial peripheral interface (SPI) ST72361xx-Auto Figure 75. Clearing the WCOL bit (write collision flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) Read SPICSR 1st Step RESULT SPIF = 0 2nd Step Read SPIDR WCOL = 0 Clearing sequence before SPIF = 1 (during a data byte transfer) Read SPICSR...
  • Page 151: Low Power Modes

    ST72361xx-Auto Serial peripheral interface (SPI) Figure 76. Single master / multiple slave configuration Slave Slave Slave Slave Device Device Device Device MOSI MISO MOSI MISO MOSI MISO MOSI MISO MOSI MISO Master Device 14.6 Low power modes Table 56. Effect of low power modes on SPI Mode Description No effect on SPI.
  • Page 152: Interrupts

    Serial peripheral interface (SPI) ST72361xx-Auto 14.7 Interrupts Table 57. SPI interrupt control and wake-up capability Enable Exit Exit Event Interrupt event control from from flag wait halt SPI End of Transfer Event SPIF Master Mode Fault Event MODF SPIE Overrun Error Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
  • Page 153: Control/Status Register (Spicsr)

    ST72361xx-Auto Serial peripheral interface (SPI) Bit 4 = MSTR Master Mode This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS = 0 (see Master mode fault (MODF)). 0: Slave mode 1: Master mode.
  • Page 154 Serial peripheral interface (SPI) ST72361xx-Auto SPIE = 1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the device and an external device has been completed.
  • Page 155: Data I/O Register (Spidr)

    ST72361xx-Auto Serial peripheral interface (SPI) 14.8.3 Data I/O register (SPIDR) Read/ write Reset value: Undefined The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Note: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer.
  • Page 156: Linsci Serial Communication Interface (Lin Master/Slave)

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) 15.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.
  • Page 157: Lin Features

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) 15.3 LIN features ● LIN master – 13-bit LIN synch break generation ● LIN slave – Automatic header handling – Automatic baud rate resynchronization based on recognition and measurement of the LIN synch field (for LIN slave nodes) –...
  • Page 158: Sci Mode - Functional Description

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Figure 77. SCI block diagram (in conventional baud rate generator mode) Write Read (DATA REGISTER) SCIDR Received Data Register (RDR) Transmit Data Register (TDR) Receive Shift Register Transmit Shift Register SCICR1 SCID M WAKE PS PIE WAKE...
  • Page 159: Extended Prescaler Mode

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) 15.5.2 Extended prescaler mode Two additional prescalers are available in extended prescaler mode. They are shown in Figure ● An extended prescaler receiver register (SCIERPR) ● An extended prescaler transmitter register (SCIETPR) 15.5.3 Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see...
  • Page 160 LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Character transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 77).
  • Page 161: Receiver

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Idle line Setting the TE bit drives the SCI to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive ‘1’s (idle line) before the first character. In this case, clearing and then setting the TE bit during a transmission sends a preamble (idle line) after the current word.
  • Page 162 LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto When an overrun error occurs: ● The OR bit is set. ● The RDR content will not be lost. ● The shift register will be overwritten. ● An interrupt is generated if the RIE bit is set and the I[|1:0] bits are cleared in the CCR register.
  • Page 163: Extended Baud Rate Generation

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register.
  • Page 164: Receiver Muting And Wake-Up Feature

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Figure 79. SCI baud rate and extended prescaler block diagram TRANSMITTER CLOCK EXTENDED PRESCALER TRANSMITTER RATE CONTROL SCIETPR EXTENDED TRANSMITTER PRESCALER REGISTER SCIERPR EXTENDED RECEIVER PRESCALER REGISTER RECEIVER CLOCK EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER TRANSMITTER RATE CONTROL...
  • Page 165: Parity Control

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Idle line detection Receiver wakes up by idle line detection when the receive line has recognized an Idle Line. Then the RWU bit is reset by hardware but the IDLE bit is not set. This feature is useful in a multiprocessor system when the first characters of the message determine the address and when each message ends by an idle line: As soon as the line becomes idle, every receivers is waken up and analyze the first characters of the message...
  • Page 166: Low Power Modes

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Example 2: data = 00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0). Odd parity The parity bit is calculated to obtain an odd number of “1s” inside the character made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
  • Page 167: Sci Mode Register Description

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 15.8 SCI mode register description 15.8.1...
  • Page 168: Control Register 1 (Scicr1)

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto The OR bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register whereas RDRF is still set. An interrupt is generated if RIE = 1 in the SCICR2 register.
  • Page 169: Control Register 2 (Scicr2)

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled Bit 4 = M Word length.
  • Page 170: Data Register (Scidr)

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software. 0: interrupt is inhibited 1: an SCI interrupt is generated whenever TC = 1 in the SCISR register Bit 5 = RIE Receiver interrupt enable.
  • Page 171: Baud Rate Register (Scibrr)

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Contains the received or transmitted data character, depending on whether it is read from or written to. The data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR).
  • Page 172: Extended Receive Prescaler Division Register (Scierpr)

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Table 64. Transmitter rate divider TR dividing factor SCT2 SCT1 SCT0 Bits 2:0 = SCR[2:0] SCI Receiver rate divider. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode.
  • Page 173: Extended Transmit Prescaler Division Register (Scietpr)

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) 15.8.7 Extended transmit prescaler division register (SCIETPR) Read/ write Reset value: 0000 0000 (00h) ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0 Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended baud rate generator is activated when a value other than 00h is stored in this register.
  • Page 174: Lin Transmission

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto In LIN Slave mode the LIN baud rate generator is selected instead of the conventional or extended prescaler. The LIN baud rate generator is common to the transmitter and the receiver. Then the baud rate can be programmed using LPR and LPRF registers. Note: It is mandatory to set the LIN configuration first before programming LPR and LPRF, because the LIN configuration uses a different baud rate generator from the standard one.
  • Page 175: Lin Reception

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Figure 81. SCI block diagram in LIN slave mode Write Read (DATA REGISTER) SCIDR Received Data Register (RDR) Transmit Data Register (TDR) Receive Shift Register Transmit Shift Register SCICR1 T8 SCID M PS PIE WAKE WAKE TRANSMIT...
  • Page 176 LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Note: It is recommended to combine the header detection function with Mute mode. Putting the LINSCI in mute mode allows the detection of Headers only and prevents the reception of any other characters. This mode can be used to wait for the next header without being interrupted by the data bytes of the current message in case this message is not relevant for the application.
  • Page 177: Lin Error Detection

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) stop bit parity bits start bit identifier bits ID1 ID2 ID3 ID4 ID5 P0 P1 Identifier Field    M = 0    15.9.4 LIN error detection LIN header error flag The LIN header error flag indicates that an invalid LIN header has been detected.
  • Page 178: Figure 82. Lin Header Reception Timeout

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto If the LHE flag is set, it means that: D > 15.625% If LHE flag is not set, it means that: D < 16.40625% If 15.625%  D  16.40625%, then the flag can be either set or reset depending on the dephasing between the signal on the RDI line and the CPU clock.
  • Page 179: Figure 83. Lin Synch Field Measurement

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) worst case: This occurs when the LIN identifier lasts exactly 10 T periods. In this BIT_MASTER case, the LIN break and synch fields last 49 - 10 = 39T periods. BIT_MASTER Assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. This leads to a maximum allowed header length of: 39 x (1/0.845) T + 10T...
  • Page 180: Lin Baud Rate

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto 15.9.5 LIN baud rate Baud rate programming is done by writing a value in the LPR prescaler or performing an automatic resynchronization as described below. Automatic resynchronization To automatically adjust the baud rate based on measurement of the LIN synch field: ●...
  • Page 181: Linsci Clock Tolerance

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Figure 84. LDIV read / write operations when LDUM = 0 Write LPFR Write LPR LIN Sync Field MANT(7:0) FRAC(3:0) LDIV_NOM Measurement Write LPR MANT(7:0) FRAC(3:0) LDIV_MEAS Update at end of Synch Field Baud Rate MANT(7:0) FRAC(3:0)
  • Page 182: Clock Deviation Causes

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Note: If the period desynchronization of the slave is +15% (slave too slow), the character “00h” which represents a sequence of 9 low bits must not be interpreted as a break character (9 bits + 15% = 10.35).
  • Page 183: Error Due To Lin Synch Measurement

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) 15.9.9 Error due to LIN synch measurement The LIN synch field is measured over eight bit times. This measurement is performed using a counter clocked by the CPU clock. The edge detections are performed using the CPU clock cycle. This leads to a precision of 2 CPU clock cycles for the measurement which lasts 16*8*LDIV clock cycles.
  • Page 184: Lin Mode Register Description

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto 15.10 LIN mode register description 15.10.1 Status register (SCISR) Read only Reset value: 1100 0000 (C0h) TDRE RDRF IDLE Bits 7:4 = same function as in SCI mode, please refer to Section 15.8: SCI mode register description.
  • Page 185: Control Register 1 (Scicr1)

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) 15.10.2 Control Register 1 (SCICR1) Read/ write Reset value: x000 0000 (x0h) SCID WAKE Bits 7:3 = Same function as in SCI mode, please refer to Section 15.8: SCI mode register description. Bit 2 = PCE Parity control enable. This bit is set and cleared by software.
  • Page 186: Control Register 3 (Scicr3)

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto 15.10.4 Control register 3 (SCICR3) Read/ write Reset value: 0000 0000 (00h) LDUM LINE LSLV LASE LHDM LHIE LHDF Bit 7 = LDUM LIN Divider Update Method. This bit is set and cleared by software and is also cleared by hardware (when RDRF = 1). It is only used in LIN Slave mode.
  • Page 187: Figure 87. Lsf Bit Set And Clear

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Bit 4 = LASE LIN Auto Synch Enable. This bit enables the Auto Synch Unit (ASU). It is set and cleared by software. It is only usable in LIN Slave mode. 0: auto synch unit disabled 1: auto synch unit enabled.
  • Page 188: Lin Divider Registers

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto 15.10.5 LIN divider registers LDIV is coded using the two registers LPR and LPFR. In LIN slave mode, the LPR register is accessible at the address of the SCIBRR register and the LPFR register is accessible at the address of the SCIETPR register.
  • Page 189: Table 68. Ldiv Fraction

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Table 68. LDIV fraction LPFR[3:0] Fraction (LDIV) 1/16 14/16 15/16 When initializing LDIV, the LPFR register must be written first. Then, the write to the LPR register will effectively update LDIV and so the clock generation. In LIN slave mode, if the LPR[7:0] register is equal to 00h, the transceiver and receiver input clocks are switched off.
  • Page 190: Lin Header Length Register (Lhlr)

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto 15.10.8 LIN header length register (LHLR) Read only Reset value: 0000 0000 (00h) LHL7 LHL6 LHL5 LHL4 LHL3 LHL2 LHL1 LHL0 Note: In LIN slave mode when LASE = 1 or LHDM = 1, the LHLR register is accessible at the address of the SCIERPR register.
  • Page 191: Table 70. Lhl Fraction Coding

    ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Table 70. LHL fraction coding LHL[1:0] Fraction (57 - T HEADER Example of LHL coding Example 1: LHL = 33h = 001100 11b LHL(7:3) = 1100b = 12d LHL(1:0) = 11b = 3d This leads to: Mantissa (57 - T ) = 12d...
  • Page 192: Table 71. Linsci1 Register Map And Reset Values

    LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Table 71. LINSCI1 register map and reset values Addr. Register name (Hex.) SCI1SR TDRE RDRF IDLE OR/LHE Reset value SCI1DR Reset value SCI1BRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 LPR (LIN Slave Mode) LPR7 LPR6 LPR5...
  • Page 193: Linsci Serial Communication Interface (Lin Master Only)

    ST72361xx-Auto LINSCI serial communication interface (LIN master only) LINSCI serial communication interface (LIN master only) 16.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format.
  • Page 194: General Description

    LINSCI serial communication interface (LIN master only) ST72361xx-Auto 16.3 General description The interface is externally connected to another device by three pins (see Figure 88: SCI block diagram). Any SCI bidirectional communication requires a minimum of two pins: Receive Data In (RDI) and Transmit Data Out (TDO): ●...
  • Page 195: Functional Description

    ST72361xx-Auto LINSCI serial communication interface (LIN master only) Figure 88. SCI block diagram Write Read (DATA REGISTER) SCIDR Received Data Register (RDR) Transmit Data Register (TDR) Received Shift Register Transmit Shift Register SCICR3 LINE CLKEN CPOL CPHA LBCL CLOCK EXTRACTION SCLK PHASE AND POLARITY CONTROL...
  • Page 196: Serial Data Format

    LINSCI serial communication interface (LIN master only) ST72361xx-Auto Refer to the register descriptions in Section 15.8: SCI mode register descriptionfor the definitions of each bit. 16.4.1 Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 89).
  • Page 197 ST72361xx-Auto LINSCI serial communication interface (LIN master only) Character transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 89).
  • Page 198: Receiver

    LINSCI serial communication interface (LIN master only) ST72361xx-Auto Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.
  • Page 199 ST72361xx-Auto LINSCI serial communication interface (LIN master only) Idle character When an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun error An overrun error occurs when a character is received when RDRF has not been reset.
  • Page 200: Conventional Baud Rate Generation

    LINSCI serial communication interface (LIN master only) ST72361xx-Auto Figure 90. SCI baud rate and extended prescaler block diagram TRANSMITTER CLOCK EXTENDED PRESCALER TRANSMITTER RATE CONTROL SCIETPR EXTENDED TRANSMITTER PRESCALER REGISTER SCIERPR EXTENDED RECEIVER PRESCALER REGISTER RECEIVER CLOCK EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER TRANSMITTER RATE CONTROL...
  • Page 201: Extended Baud Rate Generation

    ST72361xx-Auto LINSCI serial communication interface (LIN master only) RR = 1, 2, 4, 8, 16, 32, 64, 128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example 1: If f is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud.
  • Page 202: Parity Control

    LINSCI serial communication interface (LIN master only) ST72361xx-Auto Receiver wakes-up by address mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.
  • Page 203: Low Power Modes

    ST72361xx-Auto LINSCI serial communication interface (LIN master only) 16.5 Low power modes Table 73. Effect of low power modes on SCI Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
  • Page 204: Figure 91. Sci Example Of Synchronous And Asynchronous Transmission

    LINSCI serial communication interface (LIN master only) ST72361xx-Auto Note: The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled (TE and RE = 0), the SCLK and TDO pins go into high impedance state. The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter to ensure that the clock pulses function correctly.
  • Page 205: Register Description

    ST72361xx-Auto LINSCI serial communication interface (LIN master only) Figure 93. SCI data clock timing diagram (M = 1) Idle or preceding Start M = 1 (9 data bits) Idle or next transmission Stop transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data...
  • Page 206 LINSCI serial communication interface (LIN master only) ST72361xx-Auto software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: data is not received 1: received data is ready to be read Bit 4 = IDLE Idle line detect. This bit is set by hardware when an Idle Line is detected.
  • Page 207: Control Register 1 (Scicr1)

    ST72361xx-Auto LINSCI serial communication interface (LIN master only) 16.8.2 Control register 1 (SCICR1) Read/ write Reset value: x000 0000 (x0h) SCID WAKE Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M = 1. Bit 6 = T8 Transmit data bit 8.
  • Page 208: Control Register 2 (Scicr2)

    LINSCI serial communication interface (LIN master only) ST72361xx-Auto 16.8.3 Control register 2 (SCICR2) Read/ write Reset value: 0000 0000 (00h) TCIE ILIE Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: an SCI interrupt is generated whenever TDRE = 1 in the SCISR register Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software.
  • Page 209: Control Register 3 (Scicr3)

    ST72361xx-Auto LINSCI serial communication interface (LIN master only) Bit 0 = SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted Note: If the SBK bit is set to “1”...
  • Page 210: Data Register (Scidr)

    LINSCI serial communication interface (LIN master only) ST72361xx-Auto Bit 1 = CPHA Clock Phase. This bit allows the user to select the phase of the clock output on the SCLK pin. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 92 Figure 0: SCLK clock line activated in middle of data bit.
  • Page 211: Baud Rate Register (Scibrr)

    ST72361xx-Auto LINSCI serial communication interface (LIN master only) 16.8.6 Baud rate register (SCIBRR) Read/ write Reset value: 0000 0000 (00h) SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 Bits 7:6 = SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: Table 77.
  • Page 212: Extended Receive Prescaler Division Register (Scierpr)

    LINSCI serial communication interface (LIN master only) ST72361xx-Auto Table 79. Receiver rate divider RR dividing factor SCR2 SCR1 SCR0 Note: This RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR is replaced by the (RR*ERPR) dividing factor. 16.8.7 Extended receive prescaler division register (SCIERPR) Read/ write...
  • Page 213: Table 80. Baud Rate Selection

    ST72361xx-Auto LINSCI serial communication interface (LIN master only) Table 80. Baud rate selection Conditions Baud Symbol Parameter Standard Unit Accuracy rate Prescaler vs. standard Conventional Mode TR (or RR) = 128, PR = 13 ~300.48 TR (or RR) = 32, PR = 13 1200 ~1201.92 TR (or RR) = 16, PR =13...
  • Page 214: 10-Bit A/D Converter (Adc)

    10-bit A/D converter (ADC) ST72361xx-Auto 10-bit A/D converter (ADC) 17.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources.
  • Page 215: A/D Conversion

    ST72361xx-Auto 10-bit A/D converter (ADC) Figure 94. ADC block diagram CPU, ADCCSR EOC SPEED ADON SLOW AIN0 AIN1 ANALOG TO DIGITAL ANALOG CONVERTER AINx ADCDRH ADCDRL 17.3.2 A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the Chapter 8: I/O ports.
  • Page 216: Changing The Conversion Channel

    10-bit A/D converter (ADC) ST72361xx-Auto 17.3.3 Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel. 17.3.4 ADCDR consistency If an End Of Conversion event occurs after software has read the ADCDRLSB but before it...
  • Page 217: Table 83. A/D Clock Selection

    ST72361xx-Auto 10-bit A/D converter (ADC) Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by software reading the ADCDRH register or writing to any bit of the ADCCSR register. 0: conversion is not complete 1: conversion complete Bit 6 = SPEED A/D clock selection This bit is set and cleared by software.
  • Page 218: Data Register (Adcdrh)

    10-bit A/D converter (ADC) ST72361xx-Auto Table 84. ADC channel selection (continued) Channel pin AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 1. The number of channels is device dependent. Refer to the device pinout description. 17.6.2 Data register (ADCDRH) Read only Reset value: 0000 0000 (00h) Bits 7:0 = D[9:2] MSB of Analog Converted Value 17.6.3...
  • Page 219: Instruction Set

    ST72361xx-Auto Instruction set Instruction set 18.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in seven main groups: Table 86. Addressing mode groups Addressing mode Example Inherent Immediate ld A, #$55 Direct ld A, $55 Indexed ld A, ($55,X) Indirect...
  • Page 220: Inherent

    Instruction set ST72361xx-Auto Table 87. CPU addressing mode overview (continued) Pointer Pointer Length Mode Syntax Destination address size (bytes) (hex.) (hex.) Short Indirect Indexed ld A, ([$10],X) 00..1FE 00..FF byte Long Indirect Indexed ld A, ([$10.w], X) 0000..FFFF 00..FF word Relative Direct jrne loop...
  • Page 221: Immediate

    ST72361xx-Auto Instruction set 18.1.2 Immediate Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Immediate instruction Function Load Compare Bit compare AND, OR, XOR Logical operations ADC, ADD, SUB, SBC Arithmetic operations 18.1.3 Direct In direct instructions, the operands are referenced by their memory address.
  • Page 222: Indirect Indexed (Short, Long)

    Instruction set ST72361xx-Auto The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
  • Page 223: Relative Mode (Direct, Indirect)

    ST72361xx-Auto Instruction set Table 89. Instructions supporting direct, indexed, indirect and indirect indexed addressing (part 2) (continued) Short instructions only Function BSET, BRES Bit Operations BTJT, BTJF Bit Test and Jump Operations SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles CALL, JP...
  • Page 224: Using A Prebyte

    Instruction set ST72361xx-Auto Table 90. Instruction groups Description Instruction Shift and rotates SWAP Unconditional jump or call CALL CALLR NOP RET Conditional branch JRxx Interruption management TRAP HALT IRET Condition code flag modification 18.2.1 Using a prebyte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined.
  • Page 225 ST72361xx-Auto Instruction set Memo Description Function/example CALL Call subroutine Call subroutine CALLR relative Clear reg, M Arithmetic Compare tst(Reg - M) One Complement A = FFH-A reg, M Decrement dec Y reg, M HALT Halt Interrupt routine IRET Pop CC, A, X, PC return Increment inc X...
  • Page 226 Instruction set ST72361xx-Auto Memo Description Function/example Negate (2's compl) neg $10 reg, M No Operation OR operation A = A + M pop reg Pop from the Stack pop CC reg, PUSH Push onto the Stack push Y Reset carry flag C = 0 Subroutine Return Enable Interrupts...
  • Page 227: Electrical Characteristics

    ST72361xx-Auto Electrical characteristics Electrical characteristics 19.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 19.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T = 25°C and T max (given by...
  • Page 228: Absolute Maximum Ratings

    Electrical characteristics ST72361xx-Auto Figure 96. Pin input voltage ST7 PIN 19.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied.
  • Page 229: Current Characteristics

    ST72361xx-Auto Electrical characteristics 19.2.2 Current characteristics Symbol Ratings Maximum value Unit Total current into V power lines (source) Total current out of V ground lines (sink) Output current sunk by any standard I/O and control pin Output current sunk by any high sink I/O pin Output current source by any I/Os and control Injected current on V Injected current on RESET pin...
  • Page 230: Operating Conditions

    Electrical characteristics ST72361xx-Auto 19.3 Operating conditions 19.3.1 General operating conditions Symbol Parameter Conditions Unit Internal clock frequency No Flash write/ erase. Extended operating voltage Analog parameters not guaranteed. Standard operating voltage Operating voltage for flash write/ = 11.4 to 12.6V erase A Suffix version Ambient temperature range...
  • Page 231: Auxiliary Voltage Detector (Avd) Thresholds

    ST72361xx-Auto Electrical characteristics 19.3.3 Auxiliary voltage detector (AVD) thresholds Subject to general operating conditions for T Symbol Parameter Conditions Unit 10 AVDF flag toggle IT+(AVD) threshold (V rise) 01 AVDF flag toggle 4.65 IT-(AVD) threshold (V fall) AVD voltage threshold hys(AVD) IT+(AVD) IT-(AVD)
  • Page 232: Supply And Clock Managers

    Electrical characteristics ST72361xx-Auto Table 91. Supply current consumption Flash devices ROM devices Symbol Parameter Conditions Unit = 2 MHz, f = 1 MHz = 4 MHz, f = 2 MHz Supply current in RUN mode = 8 MHz, f = 4 MHz = 16 MHz, f = 8 MHz = 2 MHz, f...
  • Page 233: On-Chip Peripherals

    ST72361xx-Auto Electrical characteristics Table 92. Clock source current consumption Symbol Parameter Conditions Unit Section 20.5.1: Crystal Supply current of resonator and ceramic resonator (2)(3) DD(RES) oscillator oscillators µA PLL supply current = 5V DD(PLL) LVD supply current HALT mode, V = 5V DD(LVD) Data based on characterization results, not tested in production.
  • Page 234: Clock And Timing Characteristics

    Electrical characteristics ST72361xx-Auto 19.5 Clock and timing characteristics Subject to general operating conditions for V , and T Table 94. General timings Symbol Parameter Conditions Unit Instruction cycle time c(INST) = 8 MHz 1500 Interrupt reaction time = t v(IT) + 10 = 8 MHz 1.25...
  • Page 235: Crystal And Ceramic Resonator Oscillators

    ST72361xx-Auto Electrical characteristics 19.5.1 Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with four different crystal/ ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time.
  • Page 236: Pll Characteristics

    Electrical characteristics ST72361xx-Auto 19.5.2 PLL characteristics Operating conditions: V 3.8 to 5.5V @ T 0 to 70°C or V 4.5 to 5.5V @ T -40 to 125°C Table 97. PLL characteristics Symbol Parameter Conditions Unit = 0 to +70 ° PLL Voltage Range DD(PLL) = -40 to +125...
  • Page 237: Auto Wakeup From Halt Oscillator (Awu)

    ST72361xx-Auto Electrical characteristics 19.6 Auto wakeup from halt oscillator (AWU) Table 98. AWU oscillator characteristics Symbol Parameter Conditions Unit AWU oscillator frequency AWU oscillator startup µs RCSRT time 1. Data based on characterization results, not tested in production. Figure 102. AWU oscillator freq. @ T 25°C Ta=25C 19.7...
  • Page 238: Emc Characteristics

    Electrical characteristics ST72361xx-Auto Table 100. Dual voltage HDFlash memory (continued) Symbol Parameter Conditions Unit Data retention = 55°C years Write erase cycles = 85°C cycles Programming or erasing PROG °C temperature range ERASE 1. Data based on characterization results, not tested in production. 2.
  • Page 239: Electromagnetic Interference (Emi)

    ST72361xx-Auto Electrical characteristics Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.
  • Page 240: Table 103. Absolute Maximum Ratings

     +25°C Dynamic latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).
  • Page 241: I/O Port Pin Characteristics

    ST72361xx-Auto Electrical characteristics 19.9 I/O port pin characteristics 19.9.1 General characteristics Subject to general operating conditions for V , and T unless otherwise specified. Table 105. I/O characteristics Symbol Parameter Conditions Unit Input low level voltage 0.3 x V Input high level voltage CMOS ports 0.7 x V Schmitt trigger voltage hysteresis...
  • Page 242: Figure 103. Connecting Unused I/O Pins

    Electrical characteristics ST72361xx-Auto Figure 103. Connecting unused I/O pins ST72XXX 10k UNUSED I/O PORT UNUSED I/O PORT 10k ST72XXX Figure 104. R vs V with V Ta=-45C Ta=25C Ta=130C Figure 105. I vs V with V Ta=-45C Ta=25C Ta=130C 242/279 Doc ID 12468 Rev 3...
  • Page 243: Output Driving Current

    ST72361xx-Auto Electrical characteristics 19.9.2 Output driving current Subject to general operating conditions for V , and T unless otherwise specified. Table 106. Output driving current Symbol Parameter Conditions Unit Output low level voltage for a standard = +5 mA I/O pin when eight pins are sunk at same time = +2 mA (see...
  • Page 244: Figure 108. Typical Voh At Vdd = 5V

    Electrical characteristics ST72361xx-Auto Figure 108. Typical V at V = 5V -45°C 130°C 25°C Iio(mA) Figure 109. Typical V vs V (standard I/Os) -45°C -45°C 0.35 25°C 25°C 130°C 130°C 0.25 0.15 Vdd(V) Vdd(V) Figure 110. Typical V vs V (high-sink I/Os) -45°C -45°C...
  • Page 245: Control Pin Characteristics

    ST72361xx-Auto Electrical characteristics Figure 111. Typical V vs V -45°C 25°C 130°C -45°C 25°C 130°C Vdd(V) Vdd(V) 19.10 Control pin characteristics 19.10.1 Asynchronous RESET pin Subject to general operating conditions for V , and T unless otherwise specified. Table 107. RESET pin characteristics Symbol Parameter Conditions...
  • Page 246: Figure 112. Reset Pin Protection When Lvd Is Disabled

    Electrical characteristics ST72361xx-Auto RESET circuit design recommendations The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V max.
  • Page 247: Iccsel/ Vpp Pin

    ST72361xx-Auto Electrical characteristics Tips when using the LVD Check that all recommendations related to reset circuit have been applied (see RESET circuit design recommendations) Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709. If this cannot be done, it is recommended to put a 100 nF + 1M pull- down on the RESET pin.
  • Page 248: Timer Peripheral Characteristics

    Electrical characteristics ST72361xx-Auto 19.11 Timer peripheral characteristics Subject to general operating conditions for V , and T unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Table 109.
  • Page 249 ST72361xx-Auto Electrical characteristics Table 111. 16-bit timer characteristics (continued) Symbol Parameter Conditions Unit Timer clock period when = 8 MHz COUNTER internal clock is selected 0.250 µs Doc ID 12468 Rev 3 249/279...
  • Page 250: Communication Interface Characteristics

    Electrical characteristics ST72361xx-Auto 19.12 Communication interface characteristics 19.12.1 SPI - serial peripheral interface Subject to general operating conditions for V , and T unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Table 112.
  • Page 251: Figure 116. Spi Slave Timing Diagram With Cpha = 0

    ST72361xx-Auto Electrical characteristics Figure 116. SPI slave timing diagram with CPHA = 0 INPUT su(SS) c(SCK) h(SS) CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 w(SCKH) a(SO) w(SCKL) v(SO) h(SO) dis(SO) r(SCK) f(SCK) MISO OUTPUT MSB OUT See note 2 BIT6 OUT LSB OUT...
  • Page 252: 10-Bit Adc Characteristics

    Electrical characteristics ST72361xx-Auto Figure 118. SPI master timing diagram INPUT c(SCK) CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 w(SCKH) r(SCK) w(SCKL) f(SCK) su(MI) h(MI) MISO INPUT...
  • Page 253: Figure 119. Rain Max Vs Fadc With Cain = 0Pf

    ST72361xx-Auto Electrical characteristics 1. Data based on characterization results, not tested in production. 2. When V and V pins are not available on the pinout, the ADC refers to V and V Figure 119. R max vs f with C = 0pF 4 MHz 2 MHz...
  • Page 254: Figure 122. Power Supply Filtering

    Electrical characteristics ST72361xx-Auto Analog power supply and reference pins Depending on the MCU pin count, the package may feature separate V and V analog power supply pins. These pins supply power to the A/D converter cell and function as the high and low reference voltages for the conversion.
  • Page 255: Table 114. Adc Accuracy With F Cpu = 8 Mhz, F Adc = 4 Mhz Rain < 10Kw, Vdd = 5V

    ST72361xx-Auto Electrical characteristics ADC accuracy Table 114. ADC accuracy with f = 8 MHz, f = 4 MHz R < 10kW, V = 5V Symbol Parameter Conditions Unit Total unadjusted error Note Offset error Gain error Differential linearity error Integral linearity error 1.
  • Page 256: Figure 123. Adc Accuracy

    Electrical characteristics ST72361xx-Auto Figure 123. ADC accuracy (1) Example of an actual transfer curve Digital Result ADCDR (2) The ideal transfer curve 1023 (3) End point correlation line 1022 – ET=Total Unadjusted Error: maximum deviation 1LSB ---------------------------------------- - IDEAL 1021 1024 between the actual and the ideal transfer curves.
  • Page 257: Package Characteristics

    ST72361xx-Auto Package characteristics Package characteristics ® 20.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ®...
  • Page 258: Figure 125. 44-Pin Low Profile Quad Flat Package (10X10)

    Package characteristics ST72361xx-Auto Figure 125. 44-pin low profile quad flat package (10x10) inches Dim. 1.60 0.063 0.05 0.15 0.002 0.006 1.35 1.40 1.45 0.053 0.055 0.057 0.30 0.37 0.45 0.012 0.015 0.018 0.09 0.20 0.004 0.000 0.008 12.00 0.472 10.00 0.394 12.00 0.472...
  • Page 259: Thermal Characteristics

    ST72361xx-Auto Package characteristics 20.3 Thermal characteristics Symbol Ratings Value Unit Package thermal resistance (junction to ambient) LQFP64 °C/W thJA LQFP44 LQFP32 Power dissipation Maximum junction temperature °C Jmax 1. The maximum power dissipation is obtained from the formula P = (T ) / R .
  • Page 260: Device Configuration And Ordering Information

    Device configuration and ordering information ST72361xx-Auto Device configuration and ordering information 21.1 Introduction Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM/FASTROM). ST72361-Auto devices are ROM versions. ST72P361-Auto devices are Factory Advanced Service Technique ROM (FASTROM) versions: They are factory-programmed HDFlash devices.
  • Page 261: Table 115. Package Selection

    ST72361xx-Auto Device configuration and ordering information Caution: The PLL can be enabled only if the “OSC RANGE” (OPT11:10) bits are configured to “MP - 2~4 MHz”. Otherwise, the device functionality is not guaranteed. Static option byte 0 Static option byte 1 AFI_MAP OSCTYPE OSCRANGE...
  • Page 262: Table 116. Alternate Function Remapping 1

    Device configuration and ordering information ST72361xx-Auto Table 116. Alternate function remapping 1 AFI mapping 1 AFI_MAP(1) T16_OCMP1 on PD3 T16_OCMP2 on PD5 T16_ICAP1 on PD4 LINSCI2_SCK not available LINSCI2_TDO not available LINSCI2_RDI not available T16_OCMP1 on PB6 T16_OCMP2 on PB7 T16_ICAP1 on PC0 LINSCI2_SCK on PD3 LINSCI2_TDO on PD5...
  • Page 263 ST72361xx-Auto Device configuration and ordering information Table 119. OSCRANGE selection (continued) OSCRANGE Typical frequency range 4~8 MHz 8~16 MHz OPT1 = reserved OPT0 = RSTC RESET clock cycle selection This option bit selects the number of CPU cycles inserted during the RESET phase and when exiting HALT mode.
  • Page 264: Flash Ordering Information

    Device configuration and ordering information ST72361xx-Auto 21.2.2 Flash ordering information The following Figure 152 serves as a guide for ordering. Figure 128. ST72F361xx-Auto Flash commercial product structure Example: ST72 Product class ST72 microcontroller Family type F = Flash Sub-family type 361 = 361 sub-family Pin count K = 32 pins...
  • Page 265: Transfer Of Customer Code

    OPTION LIST appended. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics sales organization is pleased to provide detailed information on contractual points. The following Figure 153 serves as a guide for ordering.
  • Page 266: Figure 130. St72361Xx-Auto Rom Commercial Product Structure

    A = -40 °C to 85 °C C = -40 °C to 125 °C Code name Defined by STMicroelectronics. Denotes ROM code, pinout and program memory size. Tape and Reel conditioning options (left blank if Tray) TR or R = Pin 1 left-oriented...
  • Page 267 Reference/ROM Code* ............* The ROM/FASTROM code name is assigned by STMicroelectronics.
  • Page 268: Development Tools

    ST72361xx-Auto Development tools Full details of tools available for the ST7 from third party manufacturers can be obtained from the STMicroelectronics Internet site: www.st.com. Tools from isystem and hitex include C compliers, emulators and gang programmers. Note: Before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device.
  • Page 269: Important Notes

    ST72361xx-Auto Important notes Important notes 23.1 All devices 23.1.1 RESET pin protection with LVD enabled As mentioned in note 2 below Figure 135, when the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line.
  • Page 270: External Interrupt Missed

    Important notes ST72361xx-Auto If these conditions are not met, the symptom can be avoided by implementing the following sequence: PUSH CC reset flag or interrupt mask POP CC 23.1.3 External interrupt missed To avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either DDR and OR.
  • Page 271 ST72361xx-Auto Important notes LD A, PFDR AND A, #02 LD Y, A; store the level after writing to PxOR/PxDDR LD A, X; check for falling edge cp A, #02 jrne OUT TNZ Y jrne OUT LD A, sema; check the semaphore status if edge is detected CP A, #01 jrne OUT call call_routine;...
  • Page 272: Unexpected Reset Fetch

    Important notes ST72361xx-Auto PUSH CC .ext1_rt; entry to interrupt routine LD A, #$00 LD sema, A IRET 23.1.4 Unexpected reset fetch If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller does not recognize the source of the interrupt and, by default, passes the RESET vector address to the CPU.
  • Page 273: Flash/Fastrom Devices Only

    ST72361xx-Auto Important notes Figure 131. Header reception event sequence LIN Synch LIN Synch Identifier Field Break Field HEADER ID field STOP bit Critical Window Active mode is set (RWU is cleared) RDRF flag is set Figure 132. LINSCI interrupt routine @interrupt void LINSCI_IT ( void ) /* LINSCI interrupt routine */ /* clear flags */ SCISR_buffer = SCISR;...
  • Page 274 Important notes ST72361xx-Auto Occurrence The occurrence of the problem is random and proportional to the baud rate. With a transmit frequency of 19200 baud (f = 8 MHz and SCIBRR = 0xC9), the wrong break duration occurrence is around 1%. Workaround If this wrong duration is not compliant with the communication protocol in the application, software can request that an Idle line be generated before the break character.
  • Page 275: 16-Bit And 8-Bit Timer Pwm Mode

    ST72361xx-Auto Important notes 23.2.2 16-bit and 8-bit timer PWM mode In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R or OC2R register. 23.3 ROM devices only 23.3.1 16-bit timer PWM mode buffering feature change In all devices, the frequency and period of the PWM signal are controlled by comparing the counter with a 16-bit buffer updated by the OCiHR and OCiLR registers.
  • Page 276: Revision History

    Revision history ST72361xx-Auto Revision history 276/279 Doc ID 12468 Rev 3...
  • Page 277: Table 120. Document Revision History

    ST72361xx-Auto Revision history Table 120. Document revision history Date Revision Changes Initial release of ST72361-Auto datasheet (derived from ST72361 datasheet, initially released as Rev. 1 on 4 October 2005); changes from source ST72361 datasheet: Replaced TQFP with LQFP packages throughout document Added “FOR AUTOMOTIVE”...
  • Page 278 Revision history ST72361xx-Auto Table 120. Document revision history (continued) Date Revision Changes Updated “ST72361-Auto MICROCONTROLLER OPTION LIST” on page 215 as follows: - added 16K devices to FASTROM options - specified “7” as maximum number of special marking characters for TQFP32 package - replaced Standard and Automotive temperature versions with temperature ranges A and B...
  • Page 279 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

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