Figure 666. Top Level Receive Controller - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
definition can be obtained. The logical channel definition will determine the data type of the
payload and therefore will determine the destination for the payload. Decoding of the ICLC
commands from the payload is required in order to extract the interface control, rate mode
and PLL commands.
Figure 666
Clock Control Module
Line
Receiver
RxDataP
RxDataN
Edge
Detection
47.7.2.2 Edge-Detection & Auto-correlation
The edge-detection and auto-correlation are described together, as the mode setting of the
auto-correlation block impacts largely on whether the edge-detection circuitry is used or not.
The edge-detection will be performed first if required before auto-correlation.
47.7.2.2.1 Auto-correlation modes
47.7.2.2.1.1 Hunt correlation mode
On reset the Receive Controller will always come up in Hunt Correlation mode. In this mode
all the Correlators are enabled and the Receive Controller is always hunting for the
synchronization pattern. The phase enables to the external clock control module are always
high. There is no edge detection for the first bit of the synchronization pattern. Hunt
Correlation mode is considered the safest mode as the Receive Controller is always
checking for the synchronization pattern, but it is the mode that consumes the most power.
1258/2058
shows the block diagram of Uplink Controller.

Figure 666. Top Level Receive Controller

(Receive Speed)
(Transmit Speed)
Enables Phases
PHSSEL
Speed
Switch
Auto-correlation
DocID027809 Rev 4
Payload
Size Counter
Header
Extraction
8
Data Type
Decoder
16
Sel
Rate
Mode
Controller
Ping
Req/Ack
ICLC
Activation
ICLC
Strobes
Decoder
(PLL)
Rx FIFO
Data
Controller
Decoder
32-bit words
Register
Unsolicit
Map
Decoder
32-bit words