Register Descriptions - STMicroelectronics SPC572L series Reference Manual

OSC Digital Interface (XOSC)
Offset
25.3.1

Register descriptions

25.3.1.1 XOSC control register (XOSC_CTL)
Offset 00h
0 1
R 0
W
Reset – 0
16 17
R 0
W
Reset – 0
1. See the Clocking chapter for reset value.
2. These bits can be written with any value, but writes are ignored. A read returns last written value.
Field
Crystal Oscillator bypass. This bit specifies whether the oscillator should be bypassed or not.
0 Software can only set this bit. System reset is needed to reset this bit.
OSCBYP 0 Oscillator output is used as root clock.
1 EXTAL is used as root clock.
1:7 Reserved
End of Count Value. These bits specify the end of count value to be used for comparison by the
oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state.
8:15
This counting period ensures that external oscillator clock signal is stable before it can be selected by
EOCV
the system. When oscillator counter reaches the value EOCV×512, oscillator available interrupt
request is generated. The OSCCNT counter is kept under reset if oscillator bypass mode is selected.
Crystal oscillator clock interrupt mask. This bit masks the I_OSC interrupt bit.
16
0 Crystal oscillator clock interrupt is masked.
M_OSC
1 Crystal oscillator clock interrupt is enabled.
17:23 Reserved
544/2058
Table 274. XOSC memory map
00h XOSC_CTL—XOSC Control Register
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
2 2 2
0 — — —
0 0 0 0
Figure 229. XOSC_CTL register
Table 275. XOSC_CTL register field descriptions
DocID027809 Rev 4
Register
6 7 8 9
0 0
0 0 – –
22 23 24 25
2 2
— — 0
0 0 0 0
Description
Location
Section 25.3.1.1
Access: Read/Write
10 11 12 13
1
EOCV
– – – –
26 27 28 29
0 0 0 0
0 0 0 0
RM0400
14 15
– –
30 31
0 0
0 0