Figure 330. Main Status Register (Msr) - STMicroelectronics SPC572L series Reference Manual

RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
Field
26 Reserved
Freeze
This bit enables to stop the SARADC conversions at the end of current channel conversion when
SoC enters debug mode.
0 Conversions are not stopped.
27
1 When SoC enters debug mode, further conversions by SARADC analog block will be stopped.
FRZ
The ongoing channel conversion will be completed and the converted data is stored. When the
SoC exits debug mode, SDADC resumes the job that was left before halting the conversions.
Changing configuration registers during halted condition may cause a pending operation to fail
when normal operation is resumed.
28–30 Reserved
External Decode Channel Format Select (EDCSELF)
This bit selects the format for 3-bit output port ipp_decode_extch used as select line for external
30
decode channel 8:1 muxes. The last three bits of external channel number are passed as is (if
value 0) or converted to gray code (if value 1) and passed to this port.
EDCSELF
0 Binary format.
1 Gray Code format.
Power-down enable
When this bit is set, the analog module is requested to enter Power Down mode. When
31
SARADC status is PWDN, resetting this bit starts SARADC transition to IDLE mode.
PWDN
0 SARADC is in normal mode
1 SARADC has been requested to power down
36.5.1.2 Main Status Register (MSR)
Offset 0x004
0 1
R 0 0
W
Reset 0 0
16 17
R
W
Reset 0 0
1. Only available with cross-triggering unit (CTU) feature.
Table 370. MCR field descriptions(Continued)
2 3 4 5
0 0 0
0 0 0 0
18 19 20 21
CHADDR
0 0 0 0

Figure 330. Main Status Register (MSR)

DocID027809 Rev 4
Description
6 7 8 9
0 0 0
0 0 0 0
22 23 24 25
0 0
0 0 0 0
Access: User Read Only
10 11 12 13
0 0 0
0 0 0 0
26 27 28 29
0 0 0 ADCSTATUS
0 0 0 0
14 15
0
0 0
30 31
0 1
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