Register Descriptions - STMicroelectronics SPC572L series Reference Manual

Wakeup Unit (WKPU)
Address offset
0x002C
0x0030 – 0x3FFF
Note: Reserved registers will read as 0, writes will have no effect. If supported and enabled by the
SoC, a transfer error will be issued when trying to access completely reserved register
space.
69.3.2

Register descriptions

This section describes in address order all the WKPU registers. Each description includes a
standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order.
69.3.2.1 NMI Status Flag Register (NSR)
This register holds the status flags of the NMI external source pin and reset request. This
register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags
in the same register. The status flag is set whenever an NMI or reset request event is
detected. The overrun flag is set whenever an NMI or reset request event is detected and
the status flag is set (i.e. has not yet been cleared). The reset request overrun is a don't-
care since the device will be reset on the first event.
The status flags are set independently of the NDSS/RDSS bits. Therefore, these flags can
set but not generate a non-maskable interrupt or system wakeup if NWRE/RWRE = 0 or if
NDSS is set to "no request".
Note: The overrun flag is cleared by writing a '1' to the appropriate overrun bit in the NSR. If the
status bit is cleared and the overrun bit is still set, the pending interrupt will not be cleared.
Note: NIF is set when: NMI Destination Source Select is disabled (NDSS = 11) and NMI System
Wakeup Request is disabled (NWRE = 0) and an NMI input event is seen (pad4 is toggled).
Note: Also see notes in
Address: 0x0000
0 1
R 0 0
W
Reset 0 0
16 17
R
W w1c w1c
Reset 0 0
2014/2058
Table 1142. WKPU memory map(Continued)
Register
Wakeup/Interrupt Falling-Edge
Event Enable Register (WIFEER)
Section 69.3.2.2, NMI Configuration Register
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 1208. NMI Status Flag Register (NSR)
DocID027809 Rev 4
Size Supported access sizes
(bits)
32
Reserved
Access: User read/write (write 1 to clear)
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0
w1c w1c
0 0 0 0
(bits)
32 on page 2019
(NCR).
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
RM0400
Location
14 15
0 0
0 0
30 31
0 0
0 0