RM0400
LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
47.6.2.11 Tx Interrupt Enable Register (TIER)
Offset:
0030h
0
1
R
0
0
W
Reset
0
0
16
17
R
0
0
W
Reset
0
0
Field
0-13
Reserved
Tx Data Interface Not Enabled — (Mask) Enables or disables the interrupt. Tx Data Interface not
14
enabled and a frame is ready to be transmitted
0 Interrupt is disabled
TXIIE
1 Interrupt is enabled
Transmit Data FIFO Overflow Interrupt Enable.
15
0 Interrupt is disabled
TXOVIE
1 Interrupt is enabled
16-26
Reserved
Ping Response Frame Transmitted Interrupt Enable.
27
0 Interrupt is disabled
TXPNGIE
1 Interrupt is enabled
28
Reserved
Unsolicited Frame transmitted Interrupt Enable
29
0 Interrupt is disabled
TXUNSIE
1 Interrupt is enabled
ICLC Frame transmitted Interrupt Enable
30
0 Interrupt is disabled
TXICLCIE
1 Interrupt is enabled
Data Frame transmitted Interrupt Enable
31
0 Interrupt is disabled
TXDTIE
1 Interrupt is enabled
2
3
4
5
0
0
0
0
0
0
0
0
18
19
20
21
0
0
0
0
0
0
0
0
Figure 651. Tx Interrupt Enable Register (TIER)
Table 666. TIER field descriptions
DocID027809 Rev 4
6
7
8
9
0
0
0
0
0
0
0
0
22
23
24
25
0
0
0
0
0
0
0
0
Description
Access: User read/write
10
11
12
13
0
0
0
0
0
0
0
0
26
27
28
29
0
0
0
0
0
0
14
15
0
0
30
31
0
0
1239/2058
1292
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