Test Mode Select (Tms) - STMicroelectronics SPC572L series Reference Manual

GTM Development Interface (GTMDI)
42.4.6

Test Mode Select (TMS)

Test Mode Select (TMS) is an input pin used to sequence the JTAG state machine. TMS is
sampled on the rising edge of TCK.
42.5 Register definition
This section provides a detailed description of all GTMDI registers accessible to the
development tool. Individual bit-level descriptions and reset states of each register are
included.
memory-mapped and can only be accessed via the JTAG interface.
Device Identity (DID)
Reserved
GTMDI Development Control (GTMDI_DC)
GTMDI Development Status (GTMDI_DS)
Reserved
TIM Watchpoint Control 1 (GTMDI_TIM_WPC1)
TIM Watchpoint Control 2 (GTMDI_TIM_WPC2)
Reserved
TOM Watchpoint Control 1 (GTMDI_TOM_WPC1)
TOM Watchpoint Control 2 (GTMDI_TOM_WPC2)
Reserved
ATOM Watchpoint Control 1(GTMDI_ATOM_WPC1)
ATOM Watchpoint Control 2 (GTMDI_ATOM_WPC2)
Reserved
SPEA Watchpoint Control 1(GTMDI_SPEA_WPC1)
SPEA Watchpoint Control 2(GTMDI_SPEA_WPC2)
Reserved
SPEB Watchpoint Control 1 (GTMDI_SPEB_WPC1)
SPEB Watchpoint Control 2 (GTMDI_SPEB_WPC2)
Reserved
DPLL Development Control (GTMDI_DPLL_WPC1)
DPLL Watchpoint Control 1 (GTMDI_DPLL_WPC2)
DPLL Watchpoint Control 2 (GTMDI_DPLL_WPC3)
DPLL Watchpoint Control 3 (GTMDI_DPLL_WPC4)
DPLL Watchpoint Control 4 (GTMDI_DPLL_WPC5)
DPLL Data Trace Control (GTMDI_DPLL_DTC)
878/2058
Table 458 shows the GTMDI registers and index values. These registers are not
Table 458. GTMDI registers
Register
DocID027809 Rev 4
RM0400
Index Read/write
0 R
1–4 —
5 R/W
6 R
7–10 —
11 R/W
12 R/W
13–16 —
17 R/W
18 R/W
19–22 —
23 R/W
24 R/W
25–28 —
29 R/W
30 R/W
31–34 —
35 R/W
36 R/W
37–40 —
41 R/W
42 R/W
43 R/W
44 R/W
45 R/W
46 R/W