Table 326. Sample Low And Mid Address Space Flash Block Bit Mapping - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset 0x0038
0 1
R 0 0
W
Reset 0 0
16 17 18
R
W
Reset 0 0
Table 326
bits to individual flash blocks
are mapped—only LOWSEL bits 0–11 (register bits 15–4
mapped. Before any mapped block can be erased, it must be selected by writing a '1' to its
corresponding bit in one of the SELn registers. See the device configuration chapter for the
complete mapping.
Note: Values written to the SEL registers do not persist through device reset. As indicated by the
reset values shown in
blocks mapped to the register are, by default, not selected for erase.

Table 326. Sample low and mid address space flash block bit mapping

Start Address End Address
0x0040_4000 0x0040_7FFF
0x00FC_0000 0x00FC_3FFF
0x00FC_4000 0x00FC_7FFF
0x00FC_8000 0x00FC_BFFF
0x00FC_C000 0x00FC_FFFF
0x00FD_0000 0x00FD_7FFF
0x00FD_8000 0x00FD_FFFF
0x00FE_0000 0x00FE_FFFF
0x00FF_0000 0x00FF_FFFF
g. The table lists the LOWLOCK register field but the structure is identical to the LOWSEL field in
h. Register bits in Power Architecture-based microcontrollers are numbered with the most significant bit as 0. This
is not necessarily the case with register field bit numbering. The field bit numbering shown in the figure has the
least significant bit numbered as 0.
2 3 4 5
0 0 0 0
19 20 21
0 0 0 0
Figure 286. SEL0 flash control register
shows an example of a mapping of SEL0 register's LOWSEL and MIDSEL field
(g)
Figure 286, all bits are reset to '0'. As a result, after a device reset all
Size
(KB)
Register
16 0
16 0
16 0
16 1
16 1
32 0
32 1
64 0
64 0
DocID027809 Rev 4
Flash Memory Programming and Configuration
6 7 8 9
LOWSEL[13:0]
0 0 0 0
22 23 24 25
MIDSEL[15:0]
0 0 0 0
. In this case, not all bits of the LOWSEL and MIDSEL fields
LOCKn LOCKn
(1)
Register Field
Bit
LOCK0 LOWLOCK[0]
LOCK0 LOWLOCK[1]
LOCK0 LOWLOCK[2]
LOCK0 LOWLOCK[3]
LOCK0 LOWLOCK[4]
LOCK0 LOWLOCK[6]
LOCK0 LOWLOCK[7]
LOCK0 LOWLOCK[8]
LOCK0 LOWLOCK[9]
Access: User read/write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
(h)
) and MIDSEL bits 0–2 are
LOCKn
Read
DCF
Lock Bloc
Record
group k No.
DATA
(3)
(2)
Bit
16 — 0
17 1 1
18 1 2
19 1 3
20 1 4
22 1 6
23 1 7
24 1 8
25 1 9
14 15
0 0
30 31
0 0
Description
(4)
BAF
Code
(5)
Flash
4
Code Flash
4
Code Flash
4
Code Flash
Code Flash
Code Flash
Code Flash
Code Flash
Figure 286.
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