Dspi Signal Description - STMicroelectronics SPC572L series Reference Manual

RM0400
46.2

DSPI signal description

This section provides the DSPI signals description.
Table 608
Signal
PCS0/
SS
PCS[3:1]
PCS4
PCS5/
(1)
PCSS
PCS[7:6]
SIN
SOUT
SCK
1. This pin is not available for DSPI_2
46.2.1 PCS0/SS — Peripheral Chip Select/Slave Select
In master mode, the PCS0 signal is a Peripheral Chip Select output that selects which slave
device the current transmission is intended for.
In slave mode, the active low SS signal is a Slave Select input signal that allows a SPI
master to select the DSPI as the target for transmission.
46.2.2 PCS1 – PCS3 — Peripheral Chip Selects 1 – 3
PCS1 – PCS3 are Peripheral Chip Select output signals in master mode.
In slave mode, these signals are unused.
46.2.3 PCS4 — Peripheral Chip Select 4
In master mode, PCS4 is a Peripheral Chip Select output signal.
46.2.4 PCS5/PCSS — Peripheral Chip Select 5/Peripheral Chip Select Strobe
PCS5 is a Peripheral Chip Select output signal. When the DSPI is in master mode and the
MCR[PCSSE] bit is cleared, this signal selects which slave device the current transfer is
intended for.
lists the signals that may connect off chip depending on device implementation.
Table 608. DSPI signal description
Master mode: Peripheral Chip Select 0 output
Slave mode: Slave Select input
Master mode: Peripheral Chip Select 1–3
Slave mode: Unused
Master mode: Peripheral Chip Select 4
Master mode: Peripheral Chip Select 5 /
Peripheral Chip Select Strobe
Slave mode: Unused
Master mode: Peripheral Chip Select 6–7
Slave mode: Unused
Serial Data In
Serial Data Out
Master mode: Serial Clock (output)
Slave mode: Serial Clock (input)
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
Description I/O
I/O
O
O
O
O
I
O
I/O
1139/2058
1220