Dts Device Connections - STMicroelectronics SPC572L series Reference Manual

Development Trigger Semaphore (DTS)
CPU writes
DTS_SEMAPHORE
to a non-zero value
DTS_SEMAPHORE register
DTS Trigger Output (DTO)
EVTO pin
Initial conditions:
– DTS_ENABLE[DTS_EN] = 0b1
– DTS_SEMAPHORE = 0x0000_0000
64.3

DTS device connections

Figure 1105
Peripheral Bridge (PBRIDGE) for access to the registers. The PBRIDGE is connected to the
device modules through a slave port of the Crossbar bus interface (XBAR).
Module
Module
Module
The registers have limited access as described in <Cross Refs>Section 64.3.1, DTS
register access.
to the semaphore registers is limited to the cores and the eDMA module and is restricted to
only setting bits. Only an access via a Nexus Read/Write Access from an external tool can
clear bits in the semaphore registers (semaphore register bits are cleared automatically
when read via Nexus/Write Access). Similarly, the DTS_ENABLE and DTS_STARTUP
registers can only be written via a Nexus Read/Write Access.
Note: Nexus Read/Write Accesses use the core load/store bus to perform accesses, but Nexus
accesses have a different Master ID than normal core load/stores.
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Figure 1104. DTO event sequence example
Internal DTO signal
is asserted
Nexus RWA reads
DTS_SEMAPHORE,
which clears register
shows the DTS device connections. The DTS module connects to the
Figure 1105. DTS device connections
XBAR Slave Port
XBAR Master ID
Access is based on the XBAR Master ID of the accessing module. Writing
DocID027809 Rev 4
EVTO asserted
externally
Internal DTO
signal is negated
Peripheral Bus
DTS Trigger Output
XBAR Master ID
RM0400
EVTO negated
externally
DCI
(DTO)
EVTO Pin