Table 17. Reference Links To Related Information - STMicroelectronics SPC572L series Reference Manual

Device configuration
6.3.3.1 SMPU_0 configuration
This section summarizes how the module is configured in the chip. For a comprehensive
description of the SMPU module itself, see the module's dedicated chapter.
Topic
Full description
System memory map
Clocking
Power management
Logical masters
Region descriptors
RGD_WORD2 formats
6.3.3.1.1 SMPU_0 logical bus master assignments
Table 18
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Figure 7. SMPU_0 configuration

Table 17. Reference links to related information

Related module
System Memory Protection Unit (SMPU)
contains the logical bus master assignments for the SMPU_0.
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Reference
Chapter 16: System Memory Protection
Unit (SMPU)
Chapter 5: Memory map
Chapter 21: Clocking
Chapter 9: Power management
Section 6.3.3.1.1: SMPU_0 logical bus
master assignments
Section 6.3.3.1.2: Number of region
descriptors supported by SMPU_0
Section 6.3.3.1.3: RGD_WORD2 formats
supported by SMPU_0
RM0400