Table 800. Srdy_Ie Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address Offset = 0x0038
0
R
W
Reset 0
8
R
W
Reset 0
16
R
SRDY_IE15 SRDY_IE14 SRDY_IE13 SRDY_IE12 SRDY_IE11 SRDY_IE10 SRDY_IE9
W
Reset 0
24
R
SRDY_IE7
W
Reset 0
Figure 788. Slow Serial Message Ready Interrupt Enable Register (SRDY_IE)
Field
0:15 Reserved. Read returns zero
Enable for Slow Serial Message Ready Interrupt on Channels 0 to 15. These bits are writeable when
corresponding DMA enable bits are set to 0 in the Slow Serial DMA Control Register. The availability
of message is indicated via assertion of corresponding bit in Slow Serial Message Ready Status
16:31
Register irrespective of the value set in corresponding interrupt enable bit and DMA is not enabled.
SRDY_IEn
When a bit in this register is asserted, an interrupt for corresponding channel is generated.
(n = (CH-1)
to 0)
0 – Interrupt on reception of Slow Serial Messages is disabled
1 – Interrupt on reception of Slow Serial Messages is enabled
49.3.2.12 DMA Fast Message Data Read Register (DMA_FMSG_DATA)
DMA Source Size must be set to 32 bits when reading this register (DMA_FMSG_DATA) via
DMA.
1 2
0 0
9 10
0 0
17 18
0 0
25 26
SRDY_IE6 SRDY_IE5
0 0

Table 800. SRDY_IE field descriptions

3 4
0 0
11 12
0 0
19 20
0 0
27 28
SRDY_IE4 SRDY_IE3
0 0
Description
DocID027809 Rev 4
SENT Receiver (SRX)
5 6
0 0
13 14
0 0
21 22
0 0
29 30
SRDY_IE2 SRDY_IE1
0 0
Access: RW
7
0
15
0
23
SRDY_IE8
0
31
SRDY_IE0
0
1381/2058
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