Hash Algorithm - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
FCE
?
False
Hash Search
Group Table
Match
?
False
Reject Frame
Flush from FIFO
Notes:
FCE - field in RCR register (flow control enable)
I/G - Individual/Group bit in destination address (lsb in first byte received in MAC frame)
48.5.12

Hash algorithm

The hash table algorithm used in the group and individual hash filtering operates as follows.
The 48-bit destination address is mapped into one of 64 bits, represented by 64 bits stored
in GAUR, GALR (group address hash match), or IAUR, IALR (individual address hash
match). This mapping is performed by passing the 48-bit address through the on-chip 32-bit
CRC generator and selecting the six most significant bits of the CRC-encoded result to
generate a number between 0 and 63. The msb of the CRC result selects GAUR (msb = 1)
or GALR (msb = 0). The five least significant bits of the hash result select the bit within the
selected register. If the CRC generator selects a bit set in the hash table, the frame is
accepted; otherwise, it is rejected.
For example, if eight group addresses are stored in the hash table and random group
addresses are received, the hash table prevents roughly 56/64 (87.5%) of the group
address frames from reaching memory. Those that do reach memory must be further filtered
by the processor to determine if they truly contain one of the eight desired addresses.
The effectiveness of the hash table declines as the number of addresses increases.
The user must initialize the hash table registers. Use this CRC32 polynomial to compute the
hash:
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Figure 774. Ethernet address recognition—microcode decisions
Group
True
False
Pause Address
?
True
Receive Frame
DocID027809 Rev 4
Receive Address
Recognition
Individual
I/G Address
?
True
Hash Search
Individual Table
Receive Frame
True
Receive Frame
Reject Frame
Flush from FIFO
False
Exact Match
?
Match
?
False
RM0400
True
Receive Frame