STMicroelectronics SPC572L series Reference Manual page 586

Flash memory controller (PFLASH Controller)
Each instantiation of the basic calibration remap function {RMD0,..., RMD(n-1)} in
Figure 250
(LADDR in the figure), the physical start address (PADDR) and the region size (SZ). The
region size is decoded to create the appropriate address bit enables which are then applied
to the registered logical flash address. An equality comparator then compares the adjusted
logical flash address against the logical address from the calibration remap descriptor to
determine the region "hit". The hit determination is further qualified based on the bus master
number that initiated the flash access. At the same time, the logical flash address and the
physical address defined in the calibration remap descriptor are merged to form the
translated address to be used in the event of a calibration region hit. Aside from the
individual instantiations of the calibration remap descriptors, this logic examines all the
descriptor hit indicators to select the appropriate translated address.
In the absence of a region "hit" data is returned from the flash at the provided logical
address.
It should be noted in the event of overlapping remap regions, the calibration remap
descriptor with the largest number is used for the address translation, that is, if a logical
flash address hits in multiple descriptors, say CRDx and CRDy, the translated address from
CRDy is used, given y > x. This definition is selected as it minimizes the gate cost and
timing impact of the calibration remap descriptor "hit" logic.
In general, the calibration remap logic operates only on flash data accesses. However, flash
instruction references can optionally remapped while in debug modes of operation to
support the use of software breakpoints when PFCRC[IRMEN] is set.
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includes the three descriptor registers containing the logical start address
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