Functional Description - STMicroelectronics SPC572L series Reference Manual

RM0400
Table 195. DMA_TCDn_CSR field descriptions(Continued)
Field
Disable request
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0 The channel's ERQ bit is not affected
DREQ
1 The channel's ERQ bit is cleared when the major loop is complete
Enable an interrupt when major counter is half complete.
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the
INT when the current major iteration count reaches the halfway point. Specifically, the
comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point
29
interrupt request is provided to support double-buffered (aka ping-pong) schemes or other types
INTHALF
of data movement where the processor needs an early indication of the transfer's progress.
Note: If BITER is set, do not use INTHALF. Use INTMAJOR instead.
0 The half-point interrupt is disabled
1 The half-point interrupt is enabled
Enable an interrupt when major iteration count completes
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the
30
INT when the current major iteration count reaches zero.
INTMAJOR
0 The end-of-major loop interrupt is disabled
1 The end-of-major loop interrupt is enabled
Channel start
If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this
31
flag after the channel begins execution. This bit resets to zero.
START
0 The channel is not explicitly started
1 The channel is explicitly started via a software initiated service request
19.4

Functional description

This section provides a description of the DMA request sources, an overview of the
microarchitecture, and functional operation of the eDMA module.
19.4.1 eDMA microarchitecture
The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-
control descriptor local memory. Additionally, the eDMA engine is further partitioned into four
submodules:
•
eDMA engine
– Address path:
This block implements registered versions of two channel transfer control
descriptors, channel x and channel y, and manages all master bus-address
calculations. All the channels provide the same functionality. This structure allows
data transfers associated with one channel to be preempted after the completion
of a read/write sequence if a higher priority channel activation is asserted while the
first channel is active. After a channel is activated, it runs until the minor loop is
completed, unless preempted by a higher priority channel. This provides a
mechanism (enabled by DCHPRIn[ECP]) where a large data move operation can
be preempted to minimize the time another channel is blocked from execution.
When any channel is selected to execute, the contents of its TCD are read from
local memory and loaded into the address path channel x registers for a normal
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