Programmable Gain And Decimation Rate - STMicroelectronics SPC572L series Reference Manual

Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface
35.7.6

Programmable gain and decimation rate

All analog inputs can be configured to have a selectable input gain as defined in the PGAN
field description in MCR. This means the input signal is sampled and the result is amplified
by the factor determined by PGAN before providing the same to modulator.
The SDADC module is provided with a fixed input sampling clock f
grossly oversampled by the modulator in order to reduce quantization noise. To support
different passbands with a fixed sampling clock, a programmable decimation rate is
implemented. The process of decimation, to eliminate redundant data at the output while
retaining the necessary information, is controlled by the field PDR in MCR.
35.7.7 High-pass filter support
For pure AC applications, it is useful to remove any DC component in the input signal. An
optional high-pass filter is implemented which can be enabled by asserting the
MCR[HPFEN] field. The –3 dB frequency of the filter is fixed (not programmable) and is
available in the device data sheet. This high-pass filter is implemented in the decimation
filter logic of the SDADC and is applicable only to internal modulator mode.
35.7.8 Data conversion
Software Control Mechanism: The SDADC block will be in continuous conversion mode as
soon as it is enabled. The conversion data is not accurate enough for some time, depending
on the latency and output settling time specifications. This is true even when there is any
change in the configuration settings provided by MCR, change in the analog channel
selection due to mux switching time. To account for these delays, an internal timer is
implemented which counts down from a start value determined by the OSD field of OSDR.
This timer is reloaded whenever the RESET_KEY of RKR is written with 0x5AF0, which is
required to start SDADC conversion from a fresh state with a changed configuration. The
timer is stalled on reaching count '0' and asserts the SFR[CDVF] field. Once this flag is
asserted, converted data is loaded into data FIFO on every rising edge of the output clock
(f ).
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Any write access to the MCR and CSR registers will deassert the CDVF flag bit to indicate
that data coming from SDADC is not valid or corrupted. If the CDVF flag is reset, the flags
DFFF and DFORF are blocked from becoming asserted, i.e. transitioning from inactive state
to active state. If DFFF bit is already set, this means the data FIFO is already full before
CVDF deassertion.
The DFF flag bit (which not conditioned by the interrupt or DMA selection) is provided
outside which can be routed to timer module at SoC level. Wraparound Control Mechanism:
Here a wrap-around logic shall include all analog channels of the input multiplexer from
Ain("000") to Ain(CSR[ANCHSEL_WRAP]) in both Single ended and Differential ended
mode in wraparound sequence triggered by Harare or software source:
•
MCR[WRMODE] bit would enable or disable the wraparound mechanism. Clearing the
WRMODE bit automatically switches FSM back to Software control mode.
•
Every valid trigger advances the wraparound counter to next channel to be converted.
•
Wraparound Counter: An internal wraparound counter which points to analog channel
to be converted takes the initial entry value for the first loop of execution from
CSR[ANCHSEL] while entering wraparound mode. From next loop onwards the
counter wraparounds to default initial value "000". Maximum value of the counter
(wraparound value) should be programmed in CSR[ANCHSEL_WRAP] before entering
750/2058 DocID027809 Rev 4
RM0400
. The input signal is
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