STMicroelectronics SPC572L series Reference Manual page 272

Core e200z215An3 description
Table 97. Machine Check Syndrome Register (MCSR) field descriptions(Continued)
Bit Name
3
8 DC_LKERR
9:10 —
11 NMI
12 MAV
13 MEA
14 U
15 IF
16 LD
17 ST
18 G
19:20 —
21 STACK_ERR
(5)
22 IMEM_PERR
272/2058
Description
Data Cache Lock error
Indicates a cache control operation or invalidation
operation invalidated one or more lines in a locked way of
the D-Cache for certain situations. May also be set on
locked line refill error.
Reserved
NMI input pin
MCAR Address Valid
Indicates that the address contained in the MCAR was
updated by hardware to correspond to the first detected
Async Mchk error condition
MCAR holds Effective Address
If MAV = 1,MEA = 1 indicates that the MCAR contains an
effective address and MEA = 0 indicates that the MCAR
contains a physical address
User
Indicates the value captured in MCAR was generated in
user mode.
Instruction Fetch Error Report
An error occurred during the fetch of an instruction and the
instruction attempted to execute. MCSRR0 contains the
instruction address.
Load type instruction Error Report
An error occurred during the attempt to execute the load
type instruction located at the address stored in MCSRR0.
This could be due to a stack limit check error, or an
external bus error.
Store type instruction Error Report
An error occurred during the attempt to execute the store
type instruction located at the address stored in MCSRR0.
This could be due to a stack limit check error, or on certain
external bus errors.
Guarded instruction Error Report
An error occurred during the attempt to execute the load
or store type instruction located at the address stored in
MCSRR0 and the access was guarded and encountered
an error on the external bus.
Reserved
Stack Access Limit Check Error
Indicates a limit check failure on a CPU data access using
R1 in the <EA> calculation.
Instruction Mem (IMEM) Parity Error
Indicates an uncorrectable error in the IMEM on a CPU
port access.
DocID027809 Rev 4
(4)
RM0400
Exception Recoverabl
(1)
type e
Async
—
Mchk
— —
NMI —
Status —
Status —
Status —
Error
Precise
Report
Error
Precise
Report
Error
Precise
Report
Error
Precise
Report
— —
Async
Precise
Mchk
Async
Precise
Mchk