Dspi Status Register (Dspi_Sr) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Frame Size
The number of bits transferred per frame is equal to the concatenated field
0–4
{CTARn_SLAVE[FMSZ5], CTARn_SLAVE[FMSZ]} value plus 1.
FMSZ
The minimum valid FMSZ field value is 4.
Clock Polarity
5
Selects the inactive state of the Serial Communications Clock (SCK).
CPOL 0 The inactive state value of SCK is low.
1 The inactive state value of SCK is high.
Clock Phase or TSB mode. (Master and Slave mode)
Selects which edge of SCK causes data to change and which edge causes data to be captured.
Devices must have identical clock phase settings for successful communication between serial
6
devices.
CPHA
In Continuous SCK or TSB modes, the bit value is ignored and the transfers are done as if the
CPHA bit is set to 1.
0 Data is captured on the leading edge of SCK and changed on the following edge.
1 Data is changed on the leading edge of SCK and captured on the following edge.
Parity Enable
7
Enables parity bit transmission and reception for the frame.
PE 0 No parity bit included/checked.
1 Parity bit is transmitted instead of last data bit in frame, parity checked for received frame.
Parity Polarity
Controls polarity of the parity bit transmitted and checked.
8
0 Even Parity: the number of 1 bits in the transmitted frame is even. The SR[SPEF] bit is set if
PP the number of 1 bits is odd in the received frame.
1 Odd Parity: the number of 1 bits in the transmitted frame is odd. The SR[SPEF] bit is set if the
number of 1 bits is even in the received frame.
MSB of Frame Size when DSI is used in 64-bit Mode
9
The number of bits transferred per frame is equal to the concatenated field
FMSZ5
{CTARn_SLAVE[FMSZ5], CTARn_SLAVE[FMSZ]} value plus 1.
10–31
This read-only bitfield is reserved and always has the value zero.
Reserved
46.3.5

DSPI Status Register (DSPI_SR)

The status register contains DSPI status bits and interrupt/DMA request event flag bits.
Software can clear most of the flag bits in the SR by writing a '1' to them (w1c). Writing a 0 to
a flag bit has no effect. This register may not be writable in module disable mode due to the
use of power saving mechanisms.
Table 616. DSPI_CTARn_SLAVE field descriptions
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
Description
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