Clear Enable Request Register (Dma_Cerq) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Set all enable requests
1
0Set only those ERQ bits specified in the SERQ field
SAER
1Set all bits in ERQL
2–7 Set enable request
SERQ Sets the corresponding bit in ERQL
19.3.6

Clear Enable Request Register (DMA_CERQ)

The Clear Enable Request Register (DMA_CERQ) provides a simple memory-mapped
mechanism to clear a given bit in the ERQL to disable the DMA request for a given channel.
The data value on a register write causes the corresponding bit in the ERQL to be cleared.
Setting the CAER bit provides a global clear function, forcing the entire contents of the
ERQL to be cleared, disabling all DMA request inputs.
If NOP is set, the command is ignored. This allows you to write multiple-byte registers as a
32-bit word. Reads of this register return all zeroes.
Address: FC0A_0000 + 0x0019
0
R 0
W NOP
Reset 0
Field
0 0Normal operation
NOP 1No operation, ignore bits 1–7 of this register
Clear all enable requests
1
0Clear only those ERQ bits specified in the CERQ field
CAER
1Clear all bits in ERQ
2–7 Clear enable request
CERQ Clears the corresponding bit in ERQL
19.3.7 Set Enable Error Interrupt Register (DMA_SEEI)
The Set Enable Error Interrupt Register (DMA_SEEI) provides a simple memory-mapped
mechanism to set a given bit in the EEIL to enable the error interrupt for a given channel.
The data value on a register write causes the corresponding bit in the EEIL to be set. Setting
the SAEE bit provides a global set function, forcing the entire EEIL contents to be set. If the
NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a
32-bit word. Reads of this register return all zeroes.
Table 169. DMA_SERQ field descriptions(Continued)
1 2
0
CAER
0 0
Figure 124. Clear Enable Request Register (DMA_CERQ)
Table 170. DMA_CERQ field descriptions
DocID027809 Rev 4
Enhanced Direct Memory Access (eDMA)
Description
3 4
0
CERQ
0 0
Description
Access: User write-only
5 6
0 0
7
0
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