Jtag/Once Pins - STMicroelectronics SPC572L series Reference Manual

RM0400
indicate the CPU is in the debug state. Instructions may the be single-stepped by scanning
new values into the CPUSCR, and performing a OnCE go+noexit command (See
Section 57.5.6.2, OnCE Command (OCMD)
debug state (but not the debug session) to execute the instruction, and will then return to the
debug state (again indicated via the OnCE Status Register (OSR)). The debug session
remains in force until the final OnCE go+exit command is executed, at which time the CPU
will return to the previous state it was in (unless a new debug request is pending). A scan
into the CPUSCR is required prior to executing each go+exit or go+noexit OnCE command.
57.5.3

JTAG/OnCE pins

The JTAG/OnCE pin interface is used to transfer OnCE instructions and data to the OnCE
control block. Depending on the particular resource being accessed, the CPU may need to
be placed in the Debug mode. For resources outside of the CPU block and contained in the
OnCE block, the processor is not disturbed, and may continue execution. If a processor
resource is required, an internal debug request (dbg_dbgrq) may be asserted to the CPU
by the OnCE controller, and causes the CPU to finish the current instruction being executed,
save the instruction pipeline information, enter Debug mode, and wait for further commands.
Asserting dbg_dbgrq will cause the chip to temporarily exit the Waiting, Stopped or Halted
power management states.
Table 955
Signal name
1. j_tdo_en is asserted when the TAP controller is in the shift_DR or shift_IR state.
A full description of JTAG pins is provided in the JTAG Support Signals section of the Core
(e200z215An3) Core Complex Overview.
57.5.4 OnCE internal interface signals
The following paragraphs describe the OnCE interface signals to other internal blocks
associated with the OnCE controller.
57.5.4.1 CPU Debug Request (dbg_dbgrq)
The dbg_dbgrq signal is asserted by the OnCE control logic to request the CPU to enter
the debug state. It may be asserted for a number of different conditions, and causes the
CPU to finish the current instruction being executed, save the instruction pipeline
information, enter the debug mode, and wait for further commands.
details the primary JTAG/OnCE interface signals.
Table 955. JTAG/OnCE primary interface signals
j_trst_b
j_tclk
j_tms
j_tdi
j_tdo
(1)
j_tdo_en
register). The CPU will then temporarily exit the
Type
I JTAG test reset
I JTAG test clock
I JTAG test mode select
I JTAG test data input
O Test data out to master controller or pad
O Enables TDO output buffer
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e200z215An3 Core Debug Support
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