Internal Message Generation - STMicroelectronics SPC572L series Reference Manual

Nexus Aurora Router (NAR)
bus-width, 64-byte, 128-byte, 256-byte, or 384-byte, depending on block transfer mode and
block transfer size). For example, if:
•
Base address = 0x0D00_0000 (i.e. TBAHI = 0x0, TBALO = 0x0D00_0000)
•
NAR_TCR[BTM] = 1 (Block-transfer mode enabled)
•
NAR_TCR[BTS] = 00 (Block-transfer size = 64-byte)
•
NAR_TCR[MXFR] = 0x100 (max transaction count)
then the total block size would be 0x100 × 0x40 = 0x4000 bytes. The dedicated debug
address range would then be 0x0D00_0000 – 0x0D00_3FFF.
The NAR can either write to the debug space one (trace memory bus-width) word at a time,
or for improved performance, it can use a block transfer. If the BTM bit of the trace memory
bus Control Register (NAR_TCR) is set, then the NAR uses block transactions to send data
through the trace memory bus port, where the size of the block is determined by the setting
of the BTS field of the NAR_TCR.
In block transfer mode, the NAR waits until the main queue partition dedicated to the trace
memory bus port reaches a specified threshold point, determined by the BTH field of the
NAR_TCR, before initiating a block transfer. The default threshold is the size of the block
transfer. That is, a block transfer does not start until there is enough data in the associated
partition to fill the block. But it might be desirable, for bandwidth reasons or because the
associated partition is smaller than the block transfer size, to begin the transfer sooner.
Hence, based on BTH, a transfer can begin when the partition is at 25%, 50%, or 75% of the
block transfer size. This capability should be used with caution. If the Nexus client does not
generate enough new data during the transfer to fill the block, then a block transfer error
results.
The NAR generates Nexus trace write transactions for the trace memory bus port using the
address from the base address register for the first transaction and then incrementing
through the memory space. Once the programmed max number of transactions have been
sent, the NAR sets the trace memory bus overflow status bit and, if desired, asserts the
NAR event-out. At this point, the NAR can either shut down the trace memory bus port for
trace, or, if the TBW bit of the NAR_TCR is set, reset the address to the beginning of the
debug space and continue sending trace data. This allows the debugger to view the most
recent data, in cases where the buffer overflows.
When TBW bit of NAR_TCR is not set then NAR shuts down the trace memory bus port. To
restart the trace memory write again from trace memory base address, the user should write
either the NPC trace memory bus base address (TBALO/TBAHI) or the transaction count
(MXFR). The user does not have to actually change the value, but can write the same target
base address again. The NAR sees any write to one of these registers as a reconfiguration
of the trace memory bus port, and resets its internal address pointer to the base address
along with clearing the target-space-full flag.
65.5.10

Internal message generation

Generally, the NAR simply conveys Nexus messages from client to port, and does not
generate messages of its own. There are, however, certain situations when the NAR needs
to communicate directly with the debugger. Internally generated messages are added to the
queue the same as external messages. If the queue is partitioned, then internal messages
are always channeled to whichever partition is dedicated to the HBDP.
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