Table 698. Fec Register Map - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
Address offset
004h Interrupt Event Register (EIR)
008h Interrupt Mask Register (EIMR)
010h Receive Descriptor Active Register (RDAR)
014h Transmit Descriptor Active Register (TDAR)
024h Ethernet Control Register (ECR)
040h MII Management Frame Register (MMFR)
044h MII Speed Control Register (MSCR)
064h MIB Control Register (MIBC)
084h Receive Control Register (RCR)
0C4h Transmit Control Register (TCR)
0E4h Physical Address Low Register (PALR)
0E8h Physical Address High Register and Type Field (PAUR)
0ECh Opcode/Pause Duration (OPD)
118h Descriptor Individual Upper Address Register (IAUR)
11Ch Descriptor Individual Lower Address Register (IALR)
120h Descriptor Group Upper Address Register (GAUR)
124h Descriptor Group Lower Address Register (GALR)
144h Transmit FIFO Watermark (TFWR)
14Ch FIFO Receive Bound Register (FRBR)
150h FIFO Receive Start Register (FRSR)
180h Receive Descriptor Ring Start Register (ERDSR)
184h Transmit Buffer Descriptor Ring Start Register (ETDSR)
188h Receive Buffer Size Register (EMRBR)
200h Count of frames not counted correctly (RMON_T_DROP)
204h RMON Tx packet count (RMON_T_PACKETS)
208h RMON Tx broadcast packets (RMON_T_BC_PKT)
20Ch RMON Tx multicast packets (RMON_T_MC_PKT)
210h RMON Tx packets with CRC/align error (RMON_T_CRC_ALIGN)
214h RMON Tx packets < 64 bytes, good CRC (RMON_T_UNDERSIZE)
218h RMON Tx packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE)
21Ch RMON Tx packets < 64 bytes, bad CRC (RMON_T_FRAG)
220h RMON Tx packets > MAX_FL bytes, bad CRC (RMON_T_JAB)
224h RMON Tx collision count (RMON_T_COL)
228h RMON Tx 64 byte packets (RMON_T_P64)
22Ch RMON Tx 65 to 127 byte packets (RMON_T_P65TO127)
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Table 698. FEC register map

Register
DocID027809 Rev 4
RM0400
Location
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