Table 1019. L2Nsel0 Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
The L2nSEL0 register fields are described in
Field
First AND Gate Input1 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
5–0
000010Level1 MUX 1 output
FirstANDInput1 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
7–6 Reserved. Read returns 0.
First AND Gate Input 2 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
13–8
000010Level1 MUX 1 output
FirstANDInput2 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
15–14 Reserved. Read returns 0.
First AND Gate Input 3 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
21–16
000010Level1 MUX 1 output
ANDInput3 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
23–22 Reserved. Read returns 0.
First AND Gate Input 4 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
29–24
000010Level1 MUX 1 output
FirstANDInput4 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
31–30 Reserved. Read returns 0.
63.5.1.2.2 Level2 Mux state n selection 1 (L2nSEL1)
Figure 1078
1832/2058

Table 1019. L2nSEL0 register field descriptions

shows the format of the L2nSEL1 register where the state number, n = 0–7.
DocID027809 Rev 4
Table 1019.
Description
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