Master Privilege Registers (Aips_Mpra) - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset
address
0x104 Peripheral Access Control Register B (AIPS_PACRB)
0x108 Peripheral Access Control Register C (AIPS_PACRC)
0x10C Peripheral Access Control Register D (AIPS_PACRD)
0x110
0x114 Peripheral Access Control Register F (AIPS_PACRF)
0x118 Peripheral Access Control Register G (AIPS_PACRG)
0x11C Peripheral Access Control Register H (AIPS_PACRH)
15.2.1

Master Privilege Registers (AIPS_MPRA)

Each MPR specifies eight 4-bit fields defining the access privilege level associated with a
bus master in the device to the various peripherals. The register provides one field per bus
master. Each master is assigned depending on its logical master number. See
Device configuration
Address: 0x000
0 1 2 3
R
MPROT0
W
Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
The MPROTn field is defined as shown in
R
W
Field
0 Reserved, should be cleared
Master trusted for read
1
Determines whether the master is trusted for read accesses.
MTR
0 This master is not trusted for read accesses.
1 This master is trusted for read accesses.
Table 135. Peripheral bridge memory map(Continued)
Register
Reserved
for details about the master assignments to these registers.
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MPROT1 MPROT2
Figure 77. Master Privilege Register A (MPRA)
0
0
Table 136. MPROTn field descriptions
DocID027809 Rev 4
MPROT3 MPROT4
Figure 78.
1
MTR
Figure 78. MPROTn fields
Description
Peripheral Bridge
Width
(bits)
32
32
32
—
32
32
32
Access: Supervisor read/write
MPROT5 MPROT6
2
MTW
Location
on page 320
on page 320
on page 320
—
on page 320
on page 320
on page 320
Chapter 6:
MPROT7
3
MPL
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