RM0400
Field
Reset Destination Source Select
00 Reset request to RGM
RDSS
01 No reaction
10 No reaction
11 No reaction
Reset Wakeup Request Enable
RWRE
1 A set RIF bit or set ROVF bit causes a system wakeup request
0 System wakeup requests from the corresponding RIF bit are disabled
Reset Rising-edge Events Enable
RREE
1 Rising-edge event is enabled
0 Rising-edge event is disabled
Reset Falling-edge Events Enable
RFEE
1 Falling-edge event is enabled
0 Falling-edge event is disabled
Note:
Writing a '0' to both NREE[x] and NFEE[x] disables the NMI functionality completely (i.e., no
system wakeup or interrupt is generated on any pad activity).
Note:
Writing to the NCR when NIF = 1 or NOVF = 1 causes an interrupt to the destination
source/system wakeup to be generated independent of an NMI wakeup event.
69.3.2.3
Wakeup/Interrupt Status Flag Register (WISR)
This register holds the wakeup/interrupt flags.
Address: 0x0014
0
1
2
3
R 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 1210. Wakeup/Interrupt Status Flag Register (WISR)
Field
External Wakeup/Interrupt Status Flag x. This flag can be cleared only by writing a 1. Writing a 0 has
no effect. If enabled (IRER[x]), EIF[x] causes an interrupt request.
EIF[x]
1An event as defined by WIREER and WIFEER has occurred
0 No event has occurred on the pad
Note:
Status bits associated with on-chip wakeup sources are located to the left of the external
wakeup/interrupt status bits and are read only. The wakeup for these sources must be
configured and cleared at the on-chip wakeup source. Also, the configuration registers for
the external interrupts/wakeups do not have corresponding bits.
Table 1144. NCR field descriptions(Continued)
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table 1145. WISR field descriptions
Description
0 0
Description
DocID027809 Rev 4
Wakeup Unit (WKPU)
Access: User read/write (write 1 to clear)
EIF[14:4]
w1c
0 0 0 0
2017/2058
2023
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