Table 132. Xbar Memory Map - STMicroelectronics SPC572L series Reference Manual

Crossbar Switch (XBAR)
Address
offset (hex)
XBAR Priority Register Slave 0
0
(XBAR_PRS0)
10 XBAR Control Register 0 (XBAR_CRS0)
XBAR Priority Register Slave 1
100
(XBAR_PRS1)
110 XBAR Control Register 1 (XBAR_CRS1)
XBAR Priority Register Slave 2
200
(XBAR_PRS2)
210 XBAR Control Register 2 (XBAR_CRS2)
XBAR Priority Register Slave 3
300
(XBAR_PRS3)
310 XBAR Control Register 3 (XBAR_CRS3)
XBAR Priority Register Slave 4
400
(XBAR_PRS4)
410 XBAR Control Register 4 (XBAR_CRS4)
XBAR Priority Register Slave 5
500
(XBAR_PRS5)
510 XBAR Control Register 5 (XBAR_CRS5)
XBAR Priority Register Slave 6
600
(XBAR_PRS6)
610 XBAR Control Register 6 (XBAR_CRS6)
XBAR Priority Register Slave 7
700
(XBAR_PRS7)
710 XBAR Control Register 7 (XBAR_CRS7)
14.1.2.1 XBAR Priority Registers Slave (XBAR_PRSn)
The priority registers (XBAR_PRSn) set the priority of each master port on a per-slave-port
basis and reside in each slave port. The priority register can be accessed only with 32-bit
accesses. The XBAR_PRSn register is read-only; attempts to write to it have no effect on it
and result in a bus-error response to the master initiating the write.
See Section 6.3.2: Crossbar switch configuration
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Table 132. XBAR memory map

Register name
DocID027809 Rev 4
Width
Access Reset value
(in bits)
See Chip
32 R
Config
32 R/W 0000_0000h
See Chip
32 R
Config
32 R/W 0000_0000h
See Chip
32 R
Config
32 R/W 0000_0000h
See Chip
32 R
Config
32 R/W 0000_0000h
See Chip
32 R
Config
32 R/W 0000_0000h
See Chip
32 R
Config
32 R/W 0000_0000h
See Chip
32 R
Config
32 R/W 0000_0000h
See Chip
32 R
Config
32 R/W 0000_0000h
for XBAR_PRSn priority values.
RM0400
Location
on page 310
on page 313
on page 310
on page 313
on page 310
on page 313
on page 310
on page 313
on page 310
on page 313
on page 310
on page 313
on page 310
on page 313
on page 310
on page 313