Pll Digital Interface (Plldig) - STMicroelectronics SPC572L series Reference Manual

PLL Digital Interface (PLLDIG)

22 PLL Digital Interface (PLLDIG)
22.1 Introduction
The MCU provides a user interface and control over the PLL system (PLLDIG).
22.2 Block Diagram
The block diagram of the PLLDIG block is found in the "Clocking chapter" of the SPC572Lx
Reference Manual.
22.3 Features
The PLLDIG has the following features:
•
Reference clock pre-divider for finer frequency synthesis resolution.
•
Reduced frequency divider for reducing the output clock frequency without causing the
PLL to lose lock.
•
Lock detect circuitry reports when the PLL has achieved frequency lock, and
continuously monitors lock status to report loss of lock conditions.
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22.4 Modes of operation
The operating modes of the PLLs is determined by the value of PLLnCR[CLKCFG]. The
various modes of operation for the PLL are:
•
Normal mode with reference, and PLL enabled
Note: Mode changes are controlled by configuring the MC_ME Mode Configuration registers
(MC_ME_<mode>_MC).
Normal mode is defined as the mode where the clocks are driven by the PLL. When using a
crystal for the clock reference, reset should remain asserted until the oscillator has
stabilized.
22.4.1 Normal mode with reference, PLL enabled
In the normal mode, the PLL receives an input clock from the reference and the pre-divider.
The PLL multiplies the frequency to create the PLL output clock. The user must supply a
crystal that is within the appropriate frequency range, the crystal manufacturer
recommended external support circuitry and short signal route from the MCU to the crystal.
The PLL generates a non-modulated clock which drives PLL_PHI1.
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User-selectable ability to generate an interrupt request upon loss of lock.
User-selectable ability to generate a system reset upon loss of lock.
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