Register Classification For Safety - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
Address: Base + 0x013C
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Field
CMD FIFO Counter
Indicates the number of entries in the CMD FIFO.
24–27
The CMDCTR is incremented every time the command part of PUSHR is written.
CMDCTR
The CMDCTR is decremented every time a SPI command is executed (all data frames due to
current command frame have been transmitted).
Command Next Pointer
28–31
Indicates which CMD FIFO Entry is used during the next transfer.
CMDNXTPTR
The CMDNXTPTR field is updated every time SPI data due to current command have been
transmitted.
46.4

Register classification for safety

The registers of this module are classified as per safety requirements as follows:
Safety Critical: There are no safety critical registers in this module.
Safety Relevant: The register bits/fields in this category are safety relevant as any random
error in these bits will lead to unwanted interference to CPU. The registers containing these
fields must be protected by periodic CRC or equivalent check implemented at chip level.
The following register bits/fields are classified in this category:
• DSPI Module Configuration Register (DSPI_MCR)
•
DSPI Transfer Count Register (DSPI_TCR)
• DSPI Clock and Transfer Attributes Register (In Master Mode) (DSPI_CTARn)
•
DSPI Clock and Transfer Attributes Extended Register (In Master Mode)
(DSPI_CTAREn)
•
DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)
•
DSPI PUSH FIFO Register In Master Mode (DSPI_PUSHR) [0:15]
•
DSPI DSI Configuration Register 0 (DSPI_DSICR0)
•
DSPI DSI Configuration Register 1 (DSPI_DSICR1)
1178/2058
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 612. DSPI Status Register Extended (DSPI_SREX)
Table 641. DSPI_SREX field descriptions
DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 CMDCTR
0 0 0 0
Description
Access: User read-only
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
CMDNXTPTR
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
0 0