Table 522. Ecc Characteristics For Gtm Memories - STMicroelectronics SPC572L series Reference Manual

GTM101 Integration (GTMINT) Module
Memories of this block are equipped with error detection features for safety improvement.
The following procedures detect errors on memory accesses:
•
Memory write data and its address are considered in the parity bits calculation. These
parity bits are stored in that memory address as part of the written data.
• Memory read data and its address are considered in the error detection. The parity bits
are part of the data read from the specified memory address.
•
Error Correcting Code (ECC), that corrects single errors and detects double errors on
each read access
43.3.3.1 ECC Description
The Error Correcting Code (ECC) for GTM RAMs provides guaranteed single bit error
correction and double bit error detection (without correction) per accessed word. On write
accesses, the parity bits are calculated and appended to the original data bits to be written
into the specified memory address. And error detection and correction are performed on
read accesses.
Note: In case of error detection (with correction or not), no write operation is done here to fix
possible errors in the memory content.
Note: All memories must be initialized with write operations in all addresses because the ECC
parity bits need to be stored in each memory address before any read operation.
Note: GTM-IP sub-block does this initialization automatically for all memories, except for FIFO0
RAM. In this case, the user must be careful to execute writes before reads.
Table 522
correction / double error detection.
MEM
Memory number of
words
FIFO0 RAM 1024
DPLL RAM1A 96
DPLL RAM1B 384
DPLL RAM2 512
MCS0 RAM0 1024
MCS1 RAM0 1024
MCS0 RAM1 512
MCS1 RAM1 512
43.3.3.1.1 Error Correcting Code (ECC) and Syndrome Definition
This ECC is based on the Hsiao code with 7 parity bits for each data word.
Table 523
data vector width can be different for each memory, so we consider only the necessary
positions for each one, not all the table positions.
990/2058
presents a summary of GTM memories and the necessary ECCs for single error

Table 522. ECC characteristics for GTM memories

MEM
address width
(bits)
10
7
9
9
10
10
9
9
shows the definition of the syndrome field for each bit position. Note that the ECC
DocID027809 Rev 4
Uncoded data
ECC
width
(bits)
(bits)
29 7
24 7
24 7
24 7
32 7
32 7
32 7
32 7
RM0400
MEM data Matrix size
in/out (number of
(data + ECC) syndrome
(bits) results)
36 46
31 38
31 40
31 40
39 49
39 49
39 48
39 48