Table 1018. C2Pis Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
Figure 1075
vector from CPU2 with the value programmed to the C2PIS register and generates a match
signal if necessary. The typical use case would be for posedge detection on match (to
detect when the priority level is set to the compare value) or high detection while match
remains.
Offset 0x14
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The C2PIS register is described in
Field
7–0
CPU2 Priority Interrupt Selection.
CPU2
31–8 Reserved
63.5.1.2 Level2 input Mux configurations registers
At level1, the set of input Mux control registers (described in <Cross Refs>Section 63.5.1.1,
Level1 input Mux configurations registers) narrows down the large number of SPU
watchpoints to a manageable set using sixty-four 8 × 1 multiplexers. At Level2, 16 inputs are
selected for each SLU from the 64 level1 outputs using 16 64 × 1 multiplexers. Six bits per
Mux select one input out of 64 (in fact 63) inputs. Each 32-bit register configures the AND
gates of one state; therefore, eight registers are used to configure inputs for the 8 SLUs. All
the 63 inputs are static for all the eight states. Any 16 inputs can be selected from the 63
input triggers for a state.
The detail selection is shown in the
States 1–7.
1830/2058
shows the format of the C2PIS register. The SPU compares the input CPR
Figure 1075. C2PIS register format

Table 1018. C2PIS register field descriptions

DocID027809 Rev 4
Table 1018.
Description
Figure 1097 for State0. Similar logic is provided for
RM0400
Access: User read/write
8 7 6 5 4 3 2 1
CPU2
0