Table 375. Imr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
Offset 0x020
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
1. Not funtionally used, but this bit can be written by software.
2. Only available with cross-triggering unit (CTU) feature.
Field
0–26
27
28
MSKJEOC
29
MSKJECH
30
MSKNEOC
31
MSKNECH
36.5.1.6 Internal Channel Interrupt Mask Registers 0–2 (ICIMR0–ICIMR2)
The interrupt mask register to channel association is described in
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 333. Interrupt Mask Register (IMR)

Table 375. IMR field descriptions

Reserved
Write of any value has no effect; read value is always 0.
Reserved
Mask bit for JEOC
0 JEOC interrupt is disabled.
1 JEOC interrupt is enabled.
Mask bit for JECH
0 JECH interrupt is disabled.
1 JECH interrupt is enabled.
Mask bit for NEOC
0 NEOC interrupt is disabled.
1 NEOC interrupt is enabled.
Mask bit for NECH
0 NECH interrupt is disabled.
1 NECH interrupt is enabled.
DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Access: User Read/Write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
(1)
0
0 0 0 0
Table 377.
14 15
0 0
0 0
30 31
0 0
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