Features - STMicroelectronics SPC572L series Reference Manual

RM0400
46.1.2

Features

The DSPI supports the following features:
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Full-duplex, four-wire synchronous transfers.
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Master and Slave modes: data streaming operation in slave mode with continuous
slave selection.
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Buffered transmit operation with 4-entry TX FIFO buffer.
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Buffered receive operation with 4-entry RX FIFO buffer.
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Asynchronous clocking scheme for Register and Protocol interfaces.
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Individual TX and RX FIFOs disabling for low-latency updates to SPI queues.
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Visibility inside TX and RX FIFOs for debugging.
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Programmable transfer attributes on a per-frame basis:
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8 Peripheral Chip Selects, expandable to 256 with external demultiplexer.
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Deglitching support for up to 128 Peripheral Chip Selects with external demultiplexer.
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DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
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Interrupt conditions:
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Global interrupt request line.
• Modified SPI transfer formats for communication with slower peripheral devices.
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Power-saving architectural features: support for stop mode
8 transfer attribute registers along with 8 extended transfer attribute registers
serial clock with programmable polarity and phase
various programmable delays
programmable serial frame size of 4 to 64 bits, expandable by software control.
SPI frames longer than 32 bits are supported using the continuous selection
format
continuously held chip select capability
parity control
TX FIFO is not full (TFFF)
RX FIFO is not empty (RFDF)
CMD FIFO is not full (CMDFFF)
End Of Queue reached (EOQF)
TX FIFO is not full (TFFF)
CMD FIFO is not full (CMDFFF)
Transfer of current frame Complete (TCF)
Transfers due from current Command frame Complete (CMDTCF)
Transfer of current SPI frame Complete (SPITCF)
attempt to transmit with an empty Transmit FIFO (TFUF)
RX FIFO is not empty (RFDF)
frame received while Receive FIFO is full (RFOF)
SPI Parity Error (SPEF)
data present in TX FIFO while CMD FIFO is empty (TFIWF)
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Deserial Serial Peripheral Interface (DSPI)
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