Figure 320. Output Settling Delay Register (Osdr) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Data FIFO Overrun Interrupt Enable
This bit enables the SFR[DFORF] field to generate an interrupt request. The final interrupt
30
request also depends on the gating signal if enabled by the GDIGE field.
DFORIE
0 Interrupt request is disabled when data FIFO overrun condition occurs
1 Interrupt request is enabled when data FIFO overrun condition occurs
Data FIFO Full DMA/Interrupt Request Enable
This field enables the SFR[DFFF] field to generate a request. The DFFDIRS field determines
which is selected, a DMA request or an interrupt request. The final DMA/interrupt request also
31
depends on the gating signal if enabled by the GDIGE field. To have safe operation this bit
should not be set when MCR[EN]=0. Whenever MCR[EN] is cleared this bit should also be
DFFDIRE
cleared if already set and FCR[FRST] can be set to clear the previous FIFO content.
0 Interrupt/DMA request is disabled when data FIFO full condition occurs
1 Interrupt/DMA request is enabled when data FIFO full condition occurs
35.6.2.6 Output Settling Delay Register (OSDR)
The Output Settling Delay Register (OSDR) provides a delay value to qualify the converted
output data coming from the SDADC.
Offset 0x0014
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface
Table 363. RSER field descriptions(Continued)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0

Figure 320. Output Settling Delay Register (OSDR)

DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0
0 0 0 0
Access: User Read/Write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
OSD
0 0 0 0
14 15
0 0
0 0
30 31
0 0
745/2058
755